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x86: Also require MMX for __builtin_ia32_maskmovq

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MMX emulation with SEE is implemented at MMX intrinsic level, not at MMX
instruction level.  _mm_maskmove_si64 intrinsic for "MASKMOVQ mm1, mm2"
is emulated with __builtin_ia32_maskmovdqu.  Since SSE "MASKMOVQ mm1, mm2"
builtin function, __builtin_ia32_maskmovq, can't be emulated with XMM
registers, make __builtin_ia32_maskmovq also require MMX instead of SSE
only.

gcc/

	PR target/97140
	* config/i386/i386-expand.c (ix86_expand_builtin): Require MMX
	for __builtin_ia32_maskmovq.

gcc/testsuite/

	PR target/97140
	* gcc.target/i386/pr97140.c: New test.
This commit is contained in:
H.J. Lu 2020-09-21 05:33:46 -07:00
parent 88ce3d5fbb
commit 6058b874ef
2 changed files with 17 additions and 1 deletions
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8
gcc/config/i386/i386-expand.c
View File

@ -11074,11 +11074,17 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
== (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))
&& (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)
isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);
if ((bisa & OPTION_MASK_ISA_MMX) && !TARGET_MMX && TARGET_MMX_WITH_SSE)
if ((bisa & OPTION_MASK_ISA_MMX)
&& !TARGET_MMX
&& TARGET_MMX_WITH_SSE
/* NB: __builtin_ia32_maskmovq also requires MMX. */
&& fcode != IX86_BUILTIN_MASKMOVQ)
{
bisa &= ~OPTION_MASK_ISA_MMX;
bisa |= OPTION_MASK_ISA_SSE2;
}
if ((bisa & isa) != bisa || (bisa2 & isa2) != bisa2)
{
bool add_abi_p = bisa & OPTION_MASK_ISA_64BIT;

10
gcc/testsuite/gcc.target/i386/pr97140.c Normal file
View File

@ -0,0 +1,10 @@
/* { dg-do compile } */
/* { dg-options "-O2 -msse2 -mno-mmx -Wno-psabi" } */
typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__));
typedef char __v8qi __attribute__ ((__vector_size__ (8)));
void
_mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P)
{
__builtin_ia32_maskmovq ((__v8qi)__A, (__v8qi)__N, __P); /* { dg-error "needs isa option -msse -m3dnowa -mmmx" } */
}