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m32c-pragma.c (m32c_register_pragmas): Register the __far address space.
* config/m32c/m32c-pragma.c (m32c_register_pragmas): Register the __far address space. * config/m32c/m32c.h (ADDR_SPACE_FAR): New. Add support for "__far" address space for R8C and M16C processor variants. * config/m32c/m32c.c (m32c_addr_space_legitimate_address_p): New. (far_addr_space_p): New. (encode_pattern_1): Add sign and zero extend support. (m32c_hard_regno_nregs_1): Large pointers in A16 mode are SImode. (m32c_extra_constraint_p2): Add SF constraint. (m32c_legitimate_address_p): Support __far addresses. (m32c_addr_space_pointer_mode): New. (m32c_addr_space_address_mode): New. (m32c_addr_space_legitimate_address_p): New. (m32c_addr_space_legitimize_address): New. (m32c_addr_space_subset_p): New. (m32c_addr_space_convert): New. (conversions): Add __far operand patterns. (m32c_prepare_move): Force constants into registers for __far moves. (m32c_split_move): __far moves are always split. * config/m32c/addsub.md (addsi3_1): Support SImode symbols. * config/m32c/mov.md (mov<mode>_far_op1): New. (mov<mode>_far_op2): New. (movqi_op): Add __far (SF) support. (movhi_op): Likewise. (movsi_splittable): Split A1A0 also. From-SVN: r165865
This commit is contained in:
DJ Delorie
DJ Delorie
parent
bf1a7f6635
commit
5fd5d7136e
@ -1,3 +1,32 @@
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2010-10-22 DJ Delorie <dj@redhat.com>
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* config/m32c/m32c-pragma.c (m32c_register_pragmas): Register the
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__far address space.
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* config/m32c/m32c.h (ADDR_SPACE_FAR): New. Add support for
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"__far" address space for R8C and M16C processor variants.
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* config/m32c/m32c.c (m32c_addr_space_legitimate_address_p): New.
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(far_addr_space_p): New.
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(encode_pattern_1): Add sign and zero extend support.
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(m32c_hard_regno_nregs_1): Large pointers in A16 mode are SImode.
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(m32c_extra_constraint_p2): Add SF constraint.
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(m32c_legitimate_address_p): Support __far addresses.
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(m32c_addr_space_pointer_mode): New.
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(m32c_addr_space_address_mode): New.
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(m32c_addr_space_legitimate_address_p): New.
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(m32c_addr_space_legitimize_address): New.
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(m32c_addr_space_subset_p): New.
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(m32c_addr_space_convert): New.
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(conversions): Add __far operand patterns.
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(m32c_prepare_move): Force constants into registers for __far
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moves.
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(m32c_split_move): __far moves are always split.
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* config/m32c/addsub.md (addsi3_1): Support SImode symbols.
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* config/m32c/mov.md (mov<mode>_far_op1): New.
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(mov<mode>_far_op2): New.
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(movqi_op): Add __far (SF) support.
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(movhi_op): Likewise.
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(movsi_splittable): Split A1A0 also.
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2010-10-22 Artjoms Sinkarovs <artyom.shinakroff@gmail.com>
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Andrew Pinski <pinskia@gmail.com>
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@ -93,9 +93,17 @@
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case 1:
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return \"add.w %X2,%h0\;adcf.w %H0\";
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case 2:
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output_asm_insn (\"add.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"adc.w %X2,%H0\";
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if (GET_CODE (operands[2]) == SYMBOL_REF)
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{
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output_asm_insn (\"add.w #%%lo(%d2),%h0\",operands);
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return \"adc.w #%%hi(%d2),%H0\";
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}
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else
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{
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output_asm_insn (\"add.w %X2,%h0\",operands);
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operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
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return \"adc.w %X2,%H0\";
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}
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case 3:
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return \"add.w %h2,%h0\;adc.w %H2,%H0\";
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case 4:
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@ -131,4 +131,13 @@ m32c_register_pragmas (void)
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c_register_pragma ("GCC", "memregs", m32c_pragma_memregs);
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c_register_pragma (NULL, "ADDRESS", m32c_pragma_address);
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c_register_pragma (NULL, "address", m32c_pragma_address);
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/* R8C and M16C have 16-bit pointers in a 20-bit address zpace.
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M32C has 24-bit pointers in a 24-bit address space, so does not
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need far pointers, but we accept the qualifier anyway, as a
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no-op. */
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if (TARGET_A16)
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c_register_addr_space ("__far", ADDR_SPACE_FAR);
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else
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c_register_addr_space ("__far", ADDR_SPACE_GENERIC);
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}
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@ -73,6 +73,7 @@ static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
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static struct machine_function *m32c_init_machine_status (void);
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static void m32c_insert_attributes (tree, tree *);
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static bool m32c_legitimate_address_p (enum machine_mode, rtx, bool);
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static bool m32c_addr_space_legitimate_address_p (enum machine_mode, rtx, bool, addr_space_t);
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static rtx m32_function_arg (CUMULATIVE_ARGS *, enum machine_mode
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const_tree, bool);
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static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
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@ -124,6 +125,18 @@ static GTY(()) rtx patternr[30];
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#define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
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#define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
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static int
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far_addr_space_p (rtx x)
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{
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if (GET_CODE (x) != MEM)
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return 0;
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#if DEBUG0
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fprintf(stderr, "\033[35mfar_addr_space: "); debug_rtx(x);
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fprintf(stderr, " = %d\033[0m\n", MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR);
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#endif
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return MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR;
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}
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/* We do most RTX matching by converting the RTX into a string, and
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using string compares. This vastly simplifies the logic in many of
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the functions in this file.
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@ -166,6 +179,16 @@ encode_pattern_1 (rtx x)
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case CONST:
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encode_pattern_1 (XEXP (x, 0));
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break;
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case SIGN_EXTEND:
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*patternp++ = '^';
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*patternp++ = 'S';
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encode_pattern_1 (XEXP (x, 0));
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break;
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case ZERO_EXTEND:
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*patternp++ = '^';
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*patternp++ = 'Z';
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encode_pattern_1 (XEXP (x, 0));
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break;
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case PLUS:
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*patternp++ = '+';
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encode_pattern_1 (XEXP (x, 0));
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@ -553,7 +576,7 @@ m32c_hard_regno_nregs_1 (int regno, enum machine_mode mode)
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return nregs_table[regno].qi_regs;
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if (GET_MODE_SIZE (mode) <= 2)
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return nregs_table[regno].hi_regs;
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if (regno == A0_REGNO && mode == PSImode && TARGET_A16)
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if (regno == A0_REGNO && mode == SImode && TARGET_A16)
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return 2;
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if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
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return nregs_table[regno].pi_regs;
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@ -993,6 +1016,8 @@ m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
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return 0;
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}
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#define A0_OR_PSEUDO(x) (IS_REG(x, A0_REGNO) || REGNO (x) >= FIRST_PSEUDO_REGISTER)
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/* Implements EXTRA_CONSTRAINT_STR (see next function too). 'S' is
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for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
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call return values. */
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@ -1000,6 +1025,29 @@ int
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m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
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{
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encode_pattern (value);
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if (far_addr_space_p (value))
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{
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if (memcmp (str, "SF", 2) == 0)
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{
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return ( (RTX_IS ("mr")
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&& A0_OR_PSEUDO (patternr[1])
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&& GET_MODE (patternr[1]) == SImode)
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|| (RTX_IS ("m+^Sri")
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&& A0_OR_PSEUDO (patternr[4])
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&& GET_MODE (patternr[4]) == HImode)
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|| (RTX_IS ("m+^Srs")
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&& A0_OR_PSEUDO (patternr[4])
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&& GET_MODE (patternr[4]) == HImode)
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|| (RTX_IS ("m+^S+ris")
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&& A0_OR_PSEUDO (patternr[5])
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&& GET_MODE (patternr[5]) == HImode)
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|| RTX_IS ("ms")
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);
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}
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return 0;
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}
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if (memcmp (str, "Sd", 2) == 0)
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{
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/* This is the common "src/dest" address */
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@ -1067,6 +1115,10 @@ m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
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{
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return r1h_operand (value, QImode);
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}
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else if (memcmp (str, "SF", 2) == 0)
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{
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return 0;
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}
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gcc_assert (str[0] != 'S');
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@ -1837,6 +1889,11 @@ m32c_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
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if (CONSTANT_P (x))
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return 1;
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if (TARGET_A16 && GET_MODE (x) != HImode && GET_MODE (x) != SImode)
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return 0;
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if (TARGET_A24 && GET_MODE (x) != PSImode)
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return 0;
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/* Wide references to memory will be split after reload, so we must
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ensure that all parts of such splits remain legitimate
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addresses. */
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@ -1871,11 +1928,13 @@ m32c_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
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to please the assembler. */
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switch (REGNO (patternr[0]))
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{
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case A0_REGNO:
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case A1_REGNO:
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case SB_REGNO:
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case FB_REGNO:
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case SP_REGNO:
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if (TARGET_A16 && GET_MODE (x) == SImode)
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return 0;
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case A0_REGNO:
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return 1;
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default:
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@ -1884,6 +1943,10 @@ m32c_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
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return 0;
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}
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}
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if (TARGET_A16 && GET_MODE (x) == SImode)
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return 0;
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if (RTX_IS ("+ri"))
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{
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/* This is more interesting, because different base registers
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@ -2097,6 +2160,204 @@ m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
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}
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/* Return the appropriate mode for a named address pointer. */
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#undef TARGET_ADDR_SPACE_POINTER_MODE
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#define TARGET_ADDR_SPACE_POINTER_MODE m32c_addr_space_pointer_mode
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static enum machine_mode
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m32c_addr_space_pointer_mode (addr_space_t addrspace)
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{
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switch (addrspace)
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{
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case ADDR_SPACE_GENERIC:
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return TARGET_A24 ? PSImode : HImode;
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case ADDR_SPACE_FAR:
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return SImode;
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default:
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gcc_unreachable ();
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}
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}
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/* Return the appropriate mode for a named address address. */
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#undef TARGET_ADDR_SPACE_ADDRESS_MODE
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#define TARGET_ADDR_SPACE_ADDRESS_MODE m32c_addr_space_address_mode
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static enum machine_mode
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m32c_addr_space_address_mode (addr_space_t addrspace)
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{
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switch (addrspace)
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{
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case ADDR_SPACE_GENERIC:
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return TARGET_A24 ? PSImode : HImode;
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case ADDR_SPACE_FAR:
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return SImode;
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default:
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gcc_unreachable ();
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}
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}
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/* Like m32c_legitimate_address_p, except with named addresses. */
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#undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P
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#define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P \
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m32c_addr_space_legitimate_address_p
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static bool
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m32c_addr_space_legitimate_address_p (enum machine_mode mode, rtx x,
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bool strict, addr_space_t as)
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{
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if (as == ADDR_SPACE_FAR)
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{
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if (TARGET_A24)
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return 0;
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encode_pattern (x);
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if (RTX_IS ("r"))
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{
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if (GET_MODE (x) != SImode)
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return 0;
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switch (REGNO (patternr[0]))
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{
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case A0_REGNO:
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return 1;
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default:
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if (IS_PSEUDO (patternr[0], strict))
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return 1;
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return 0;
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}
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}
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if (RTX_IS ("+^Sri"))
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{
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int rn = REGNO (patternr[3]);
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HOST_WIDE_INT offs = INTVAL (patternr[4]);
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if (GET_MODE (patternr[3]) != HImode)
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return 0;
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switch (rn)
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{
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case A0_REGNO:
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return (offs >= 0 && offs <= 0xfffff);
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default:
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if (IS_PSEUDO (patternr[3], strict))
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return 1;
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return 0;
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}
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}
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if (RTX_IS ("+^Srs"))
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{
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int rn = REGNO (patternr[3]);
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if (GET_MODE (patternr[3]) != HImode)
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return 0;
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switch (rn)
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{
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case A0_REGNO:
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return 1;
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default:
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if (IS_PSEUDO (patternr[3], strict))
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return 1;
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return 0;
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}
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}
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if (RTX_IS ("+^S+ris"))
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{
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int rn = REGNO (patternr[4]);
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if (GET_MODE (patternr[4]) != HImode)
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return 0;
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switch (rn)
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{
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case A0_REGNO:
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return 1;
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default:
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if (IS_PSEUDO (patternr[4], strict))
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return 1;
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return 0;
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}
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}
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if (RTX_IS ("s"))
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{
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return 1;
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}
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return 0;
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}
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else if (as != ADDR_SPACE_GENERIC)
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gcc_unreachable ();
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return m32c_legitimate_address_p (mode, x, strict);
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}
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/* Like m32c_legitimate_address, except with named address support. */
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#undef TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS
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#define TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS m32c_addr_space_legitimize_address
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static rtx
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m32c_addr_space_legitimize_address (rtx x, rtx oldx, enum machine_mode mode,
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addr_space_t as)
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{
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if (as != ADDR_SPACE_GENERIC)
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{
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#if DEBUG0
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fprintf (stderr, "\033[36mm32c_addr_space_legitimize_address for mode %s\033[0m\n", mode_name[mode]);
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debug_rtx (x);
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fprintf (stderr, "\n");
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#endif
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if (GET_CODE (x) != REG)
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{
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x = force_reg (SImode, x);
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}
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return x;
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}
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return m32c_legitimize_address (x, oldx, mode);
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}
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/* Determine if one named address space is a subset of another. */
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#undef TARGET_ADDR_SPACE_SUBSET_P
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#define TARGET_ADDR_SPACE_SUBSET_P m32c_addr_space_subset_p
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static bool
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m32c_addr_space_subset_p (addr_space_t subset, addr_space_t superset)
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{
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gcc_assert (subset == ADDR_SPACE_GENERIC || subset == ADDR_SPACE_FAR);
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gcc_assert (superset == ADDR_SPACE_GENERIC || superset == ADDR_SPACE_FAR);
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if (subset == superset)
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return true;
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else
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return (subset == ADDR_SPACE_GENERIC && superset == ADDR_SPACE_FAR);
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}
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#undef TARGET_ADDR_SPACE_CONVERT
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#define TARGET_ADDR_SPACE_CONVERT m32c_addr_space_convert
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/* Convert from one address space to another. */
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static rtx
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m32c_addr_space_convert (rtx op, tree from_type, tree to_type)
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{
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addr_space_t from_as = TYPE_ADDR_SPACE (TREE_TYPE (from_type));
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addr_space_t to_as = TYPE_ADDR_SPACE (TREE_TYPE (to_type));
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rtx result;
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gcc_assert (from_as == ADDR_SPACE_GENERIC || from_as == ADDR_SPACE_FAR);
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gcc_assert (to_as == ADDR_SPACE_GENERIC || to_as == ADDR_SPACE_FAR);
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if (to_as == ADDR_SPACE_GENERIC && from_as == ADDR_SPACE_FAR)
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{
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/* This is unpredictable, as we're truncating off usable address
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bits. */
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result = gen_reg_rtx (HImode);
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emit_move_insn (result, simplify_subreg (HImode, op, SImode, 0));
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return result;
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}
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else if (to_as == ADDR_SPACE_FAR && from_as == ADDR_SPACE_GENERIC)
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{
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/* This always works. */
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result = gen_reg_rtx (SImode);
|
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emit_insn (gen_zero_extendhisi2 (result, op));
|
||||
return result;
|
||||
}
|
||||
else
|
||||
gcc_unreachable ();
|
||||
}
|
||||
|
||||
/* Condition Code Status */
|
||||
|
||||
#undef TARGET_FIXED_CONDITION_CODE_REGS
|
||||
@ -2350,6 +2611,12 @@ const conversions[] = {
|
||||
{ 0, "mr", "z[1]" },
|
||||
{ 0, "m+ri", "3[2]" },
|
||||
{ 0, "m+rs", "3[2]" },
|
||||
{ 0, "m+^Zrs", "5[4]" },
|
||||
{ 0, "m+^Zri", "5[4]" },
|
||||
{ 0, "m+^Z+ris", "7+6[5]" },
|
||||
{ 0, "m+^Srs", "5[4]" },
|
||||
{ 0, "m+^Sri", "5[4]" },
|
||||
{ 0, "m+^S+ris", "7+6[5]" },
|
||||
{ 0, "m+r+si", "4+5[2]" },
|
||||
{ 0, "ms", "1" },
|
||||
{ 0, "mi", "1" },
|
||||
@ -3392,6 +3659,11 @@ m32c_subreg (enum machine_mode outer,
|
||||
int
|
||||
m32c_prepare_move (rtx * operands, enum machine_mode mode)
|
||||
{
|
||||
if (far_addr_space_p (operands[0])
|
||||
&& CONSTANT_P (operands[1]))
|
||||
{
|
||||
operands[1] = force_reg (GET_MODE (operands[0]), operands[1]);
|
||||
}
|
||||
if (TARGET_A16 && mode == PSImode)
|
||||
return m32c_split_move (operands, mode, 1);
|
||||
if ((GET_CODE (operands[0]) == MEM)
|
||||
@ -3497,6 +3769,11 @@ m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
|
||||
if (m32c_extra_constraint_p (operands[0], 'S', "Ss"))
|
||||
split_all = 3;
|
||||
|
||||
if (TARGET_A16
|
||||
&& (far_addr_space_p (operands[0])
|
||||
|| far_addr_space_p (operands[1])))
|
||||
split_all |= 1;
|
||||
|
||||
/* We don't need to split these. */
|
||||
if (TARGET_A24
|
||||
&& split_all != 3
|
||||
|
||||
@ -567,6 +567,10 @@ typedef struct m32c_cumulative_args
|
||||
|
||||
#define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X)
|
||||
|
||||
/* Address spaces. */
|
||||
#define ADDR_SPACE_FAR 1
|
||||
|
||||
|
||||
/* Condition Code Status */
|
||||
|
||||
#define REVERSIBLE_CC_MODE(MODE) 1
|
||||
|
||||
@ -28,22 +28,45 @@
|
||||
;; example is code like this: a = *b where both a and b are spilled to
|
||||
;; the stack.
|
||||
|
||||
(define_insn "mov<mode>_far_op1"
|
||||
[(set (match_operand:QHI 0 "register_operand" "=Rhi")
|
||||
(mem:QHI (plus:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "Ra0"))
|
||||
(match_operand 2 "immediate_operand" "si"))))
|
||||
]
|
||||
""
|
||||
"lde.<bwl>\t%D2[%1],%0"
|
||||
[(set_attr "flags" "sz")]
|
||||
)
|
||||
|
||||
(define_insn "mov<mode>_far_op2"
|
||||
[(set (mem:QHI (plus:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "Ra0"))
|
||||
(match_operand 1 "immediate_operand" "si")))
|
||||
(match_operand:QHI 2 "register_operand"
|
||||
"=Rhi"))
|
||||
]
|
||||
""
|
||||
"ste.<bwl>\t%2,%D1[%0]"
|
||||
[(set_attr "flags" "sz")]
|
||||
)
|
||||
|
||||
;; Match push/pop before mov.b for passing char as arg,
|
||||
;; e.g. stdlib/efgcvt.c.
|
||||
(define_insn "movqi_op"
|
||||
[(set (match_operand:QI 0 "m32c_nonimmediate_operand"
|
||||
"=Rqi*Rmm, <, RqiSd*Rmm, SdSs, Rqi*Rmm, Sd")
|
||||
"=SF,Rhi*Rmm, Rqi*Rmm, <, RqiSd*Rmm, SdSs, Rqi*Rmm, Sd")
|
||||
(match_operand:QI 1 "m32c_any_operand"
|
||||
"iRqi*Rmm, iRqiSd*Rmm, >, Rqi*Rmm, SdSs, i"))]
|
||||
"Rhi*Rmm,SF, iRqi*Rmm, iRqiSd*Rmm, >, Rqi*Rmm, SdSs, i"))]
|
||||
"m32c_mov_ok (operands, QImode)"
|
||||
"@
|
||||
lde.b\t%1,%0
|
||||
ste.b\t%1,%0
|
||||
mov.b\t%1,%0
|
||||
push.b\t%1
|
||||
pop.b\t%0
|
||||
mov.b\t%1,%0
|
||||
mov.b\t%1,%0
|
||||
mov.b\t%1,%0"
|
||||
[(set_attr "flags" "sz,*,*,sz,sz,sz")]
|
||||
[(set_attr "flags" "sz,sz,sz,*,*,sz,sz,sz")]
|
||||
)
|
||||
|
||||
(define_expand "movqi"
|
||||
@ -56,11 +79,13 @@
|
||||
|
||||
(define_insn "movhi_op"
|
||||
[(set (match_operand:HI 0 "m32c_nonimmediate_operand"
|
||||
"=Rhi*Rmm, Sd, SdSs, *Rcr, RhiSd*Rmm, <, RhiSd*Rmm, <, *Rcr")
|
||||
"=SF,Rhi*Rmm, Rhi*Rmm, Sd, SdSs, *Rcr, RhiSd*Rmm, <, RhiSd*Rmm, <, *Rcr")
|
||||
(match_operand:HI 1 "m32c_any_operand"
|
||||
"iRhi*RmmSdSs, i, Rhi*Rmm, RhiSd*Rmm, *Rcr, iRhiSd*Rmm, >, *Rcr, >"))]
|
||||
" Rhi*Rmm,SF, iRhi*RmmSdSs, i, Rhi*Rmm, RhiSd*Rmm, *Rcr, iRhiSd*Rmm, >, *Rcr, >"))]
|
||||
"m32c_mov_ok (operands, HImode)"
|
||||
"@
|
||||
ste.w\t%1,%0
|
||||
lde.w\t%1,%0
|
||||
mov.w\t%1,%0
|
||||
mov.w\t%1,%0
|
||||
mov.w\t%1,%0
|
||||
@ -70,7 +95,7 @@
|
||||
pop.w\t%0
|
||||
pushc\t%1
|
||||
popc\t%0"
|
||||
[(set_attr "flags" "sz,sz,sz,n,n,n,n,n,n")]
|
||||
[(set_attr "flags" "sz,sz,sz,sz,sz,n,n,n,n,n,n")]
|
||||
)
|
||||
|
||||
(define_expand "movhi"
|
||||
@ -176,11 +201,11 @@
|
||||
|
||||
; All SI moves are split if TARGET_A16
|
||||
(define_insn_and_split "movsi_splittable"
|
||||
[(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=Rsi<*Rmm,RsiSd*Rmm,Ss")
|
||||
(match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm,iRsi>*Rmm,Rsi*Rmm"))]
|
||||
[(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiRaa<*Rmm, RsiRaaSd*Rmm, Ss")
|
||||
(match_operand:SI 1 "m32c_any_operand" "iRsiRaaSd*Rmm, iRsiRaa>*Rmm, RsiRaa*Rmm"))]
|
||||
"TARGET_A16"
|
||||
"#"
|
||||
"TARGET_A16 && reload_completed"
|
||||
"TARGET_A16"
|
||||
[(pc)]
|
||||
"m32c_split_move (operands, SImode, 1); DONE;"
|
||||
)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user