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Rename -mshort-load-bytes switch to -malignment-traps
From-SVN: r30604
This commit is contained in:
Nick Clifton
parent
5b8ad69915
commit
5f1e6755ec
@ -1,4 +1,17 @@
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Fro Nov 19 05:48:45 CET 1999 Jan Hubicka <hubicka@freesoft.cz>
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1999-11-21 Nick Clifton <nickc@cygnus.com>
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* invoke.texi (ARM Options): Replace -mshort-load-bytes with
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-malignment-traps.
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(arm.h): Replace -mshort-load-bytes with -malignment-traps.
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(arm.c): Replace TARGET_SHORT_BY_BYTES with TARGET_MMU_TRAPS.
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(arm.md): Replace TARGET_SHORT_BY_BYTES with TARGET_MMU_TRAPS.
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Sun Nov 21 17:11:13 1999 Geoffrey Keating <geoffk@cygnus.com>
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* varasm.c (output_constructor): Solve problem with long long
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bitfields, even on BYTES_BIG_ENDIAN machines (testcase 991118-1).
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Fri Nov 19 05:48:45 CET 1999 Jan Hubicka <hubicka@freesoft.cz>
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* global.c (allocno): New structure and static variable.
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(allocno_reg): Remove, all references replaced by allocno.
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@ -25,11 +38,6 @@ Fro Nov 19 05:48:45 CET 1999 Jan Hubicka <hubicka@freesoft.cz>
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pass rtl_dump_file to regclass.
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* rtl.h (regclass): Update prototype.
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Sun Nov 21 17:11:13 1999 Geoffrey Keating <geoffk@cygnus.com>
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* varasm.c (output_constructor): Solve problem with long long
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bitfields, even on BYTES_BIG_ENDIAN machines (testcase 991118-1).
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Fri Nov 19 06:32:19 CET 1999 Jan Hubicka <hubicka@freesoft.cz>
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* i386.md (neg, not and abs patterns): Revmap to use
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@ -3483,7 +3483,7 @@ gen_rotated_half_load (memref)
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}
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/* If we aren't allowed to generate unaligned addresses, then fail. */
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if (TARGET_SHORT_BY_BYTES
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if (TARGET_MMU_TRAPS
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&& ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
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return NULL;
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@ -285,9 +285,9 @@ Unrecognized value in TARGET_CPU_DEFAULT.
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This is equivalent to -fpic. */
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#define ARM_FLAG_APCS_REENT (1 << 6)
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/* Nonzero if the MMU will trap unaligned word accesses, so shorts must be
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loaded byte-at-a-time. */
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#define ARM_FLAG_SHORT_BYTE (1 << 7)
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/* Nonzero if the MMU will trap unaligned word accesses, so shorts must
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be loaded using either LDRH or LDRB instructions. */
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#define ARM_FLAG_MMU_TRAPS (1 << 7)
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/* Nonzero if all floating point instructions are missing (and there is no
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emulator either). Generate function calls for all ops in this case. */
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@ -323,14 +323,7 @@ Unrecognized value in TARGET_CPU_DEFAULT.
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#define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
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#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
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#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
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/* Note: TARGET_SHORT_BY_BYTES is really a misnomer. What it means is
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that short values should not be accessed using word load instructions
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as there is a possibility that they may not be word aligned and this
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would generate an MMU fault. On processors which do not have a 16 bit
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load instruction therefore, short values must be loaded by individual
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byte accesses rather than loading a word and then shifting the desired
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value into place. */
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#define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE)
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#define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
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#define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
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#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
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#define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
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@ -369,12 +362,13 @@ Unrecognized value in TARGET_CPU_DEFAULT.
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{"apcs-reentrant", ARM_FLAG_APCS_REENT, \
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"Generate re-entrant, PIC code" }, \
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{"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
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{"short-load-bytes", ARM_FLAG_SHORT_BYTE, \
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"Load shorts a byte at a time" }, \
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{"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE, "" }, \
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{"short-load-words", -ARM_FLAG_SHORT_BYTE, \
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"Load words a byte at a time" }, \
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{"no-short-load-words", ARM_FLAG_SHORT_BYTE, "" }, \
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{"alignment-traps", ARM_FLAG_MMU_TRAPS, \
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"The MMU will trap on unaligned accesses" },\
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{"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
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{"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
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{"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
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{"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
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{"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
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{"soft-float", ARM_FLAG_SOFT_FLOAT, \
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"Use library calls to perform FP operations" }, \
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{"hard-float", -ARM_FLAG_SOFT_FLOAT, \
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@ -540,7 +534,7 @@ extern int arm_is_6_or_7;
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if (MODE == QImode) \
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UNSIGNEDP = 1; \
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else if (MODE == HImode) \
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UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
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UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
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(MODE) = SImode; \
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}
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@ -1002,7 +996,7 @@ enum reg_class
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/* If we need to load shorts byte-at-a-time, then we need a scratch. */
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#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
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(((MODE) == HImode && ! arm_arch4 && TARGET_SHORT_BY_BYTES \
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(((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
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&& (GET_CODE (X) == MEM \
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|| ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
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&& true_regnum (X) == -1))) \
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@ -2441,7 +2441,7 @@
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{
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if (arm_arch4 && GET_CODE (operands[1]) == MEM)
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{
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/* Note: We do not have to worry about TARGET_SHORT_BY_BYTES
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/* Note: We do not have to worry about TARGET_MMU_TRAPS
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here because the insn below will generate an LDRH instruction
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rather than an LDR instruction, so we cannot get an unaligned
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word access. */
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@ -2449,7 +2449,7 @@
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gen_rtx_ZERO_EXTEND (SImode, operands[1])));
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DONE;
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}
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if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM)
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if (TARGET_MMU_TRAPS && GET_CODE (operands[1]) == MEM)
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{
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emit_insn (gen_movhi_bytes (operands[0], operands[1]));
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DONE;
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@ -2549,7 +2549,7 @@
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{
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if (arm_arch4 && GET_CODE (operands[1]) == MEM)
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{
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/* Note: We do not have to worry about TARGET_SHORT_BY_BYTES
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/* Note: We do not have to worry about TARGET_MMU_TRAPS
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here because the insn below will generate an LDRH instruction
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rather than an LDR instruction, so we cannot get an unaligned
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word access. */
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@ -2558,7 +2558,7 @@
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DONE;
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}
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if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM)
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if (TARGET_MMU_TRAPS && GET_CODE (operands[1]) == MEM)
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{
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emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
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DONE;
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@ -3184,13 +3184,13 @@
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}
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else if (! arm_arch4)
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{
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/* Note: We do not have to worry about TARGET_SHORT_BY_BYTES
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/* Note: We do not have to worry about TARGET_MMU_TRAPS
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for v4 and up architectures because LDRH instructions will
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be used to access the HI values, and these cannot generate
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unaligned word access faults in the MMU. */
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if (GET_CODE (operands[1]) == MEM)
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{
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if (TARGET_SHORT_BY_BYTES)
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if (TARGET_MMU_TRAPS)
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{
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rtx base;
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rtx offset = const0_rtx;
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@ -3289,7 +3289,7 @@
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(rotate:SI (match_operand:SI 1 "offsettable_memory_operand" "o")
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(const_int 16)))]
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"! TARGET_SHORT_BY_BYTES"
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"! TARGET_MMU_TRAPS"
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"*
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{
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rtx ops[2];
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@ -3373,7 +3373,7 @@
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(match_operand:HI 1 "general_operand" "rI,K,m"))]
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"! arm_arch4
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&& ! BYTES_BIG_ENDIAN
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&& ! TARGET_SHORT_BY_BYTES
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&& ! TARGET_MMU_TRAPS
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&& (GET_CODE (operands[1]) != CONST_INT
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|| const_ok_for_arm (INTVAL (operands[1]))
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|| const_ok_for_arm (~INTVAL (operands[1])))"
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@ -3389,7 +3389,7 @@
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(match_operand:HI 1 "general_operand" "rI,K,m"))]
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"! arm_arch4
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&& BYTES_BIG_ENDIAN
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&& ! TARGET_SHORT_BY_BYTES
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&& ! TARGET_MMU_TRAPS
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&& (GET_CODE (operands[1]) != CONST_INT
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|| const_ok_for_arm (INTVAL (operands[1]))
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|| const_ok_for_arm (~INTVAL (operands[1])))"
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@ -3406,7 +3406,7 @@
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(rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand" "m") 0)
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(const_int 16)))]
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"BYTES_BIG_ENDIAN
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&& ! TARGET_SHORT_BY_BYTES"
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&& ! TARGET_MMU_TRAPS"
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"ldr%?\\t%0, %1\\t%@ movhi_bigend"
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[(set_attr "type" "load")
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(set_attr "pool_range" "4096")])
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@ -3414,7 +3414,7 @@
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(define_insn "*movhi_bytes"
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[(set (match_operand:HI 0 "s_register_operand" "=r,r")
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(match_operand:HI 1 "arm_rhs_operand" "rI,K"))]
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"TARGET_SHORT_BY_BYTES"
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"TARGET_MMU_TRAPS"
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"@
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mov%?\\t%0, %1\\t%@ movhi
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mvn%?\\t%0, #%B1\\t%@ movhi")
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@ -3436,7 +3436,7 @@
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[(parallel [(match_operand:HI 0 "s_register_operand" "=r")
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(match_operand:HI 1 "reload_memory_operand" "o")
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(match_operand:DI 2 "s_register_operand" "=&r")])]
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"TARGET_SHORT_BY_BYTES"
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"TARGET_MMU_TRAPS"
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"
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arm_reload_in_hi (operands);
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DONE;
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@ -5932,7 +5932,7 @@
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (match_dup 1) (match_dup 2)))]
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"(! BYTES_BIG_ENDIAN)
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&& ! TARGET_SHORT_BY_BYTES
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&& ! TARGET_MMU_TRAPS
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&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
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&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
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&& (GET_CODE (operands[2]) != REG
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@ -5947,7 +5947,7 @@
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"(!BYTES_BIG_ENDIAN)
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&& ! TARGET_SHORT_BY_BYTES
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&& ! TARGET_MMU_TRAPS
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&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
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&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
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&& (GET_CODE (operands[2]) != REG
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@ -6085,7 +6085,7 @@
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(plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
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(match_dup 1)))]
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"(! BYTES_BIG_ENDIAN)
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&& ! TARGET_SHORT_BY_BYTES
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&& ! TARGET_MMU_TRAPS
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&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
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&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
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&& REGNO (operands[3]) != FRAME_POINTER_REGNUM"
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@ -6102,7 +6102,7 @@
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(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
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(match_dup 4)])))]
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"(! BYTES_BIG_ENDIAN)
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&& ! TARGET_SHORT_BY_BYTES
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&& ! TARGET_MMU_TRAPS
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&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
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&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
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&& REGNO (operands[3]) != FRAME_POINTER_REGNUM"
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@ -6149,7 +6149,7 @@
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(set (match_dup 1)
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(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
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"(! BYTES_BIG_ENDIAN)
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&& ! TARGET_SHORT_BY_BYTES
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&& ! TARGET_MMU_TRAPS
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&& REGNO(operands[0]) != REGNO(operands[1])
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&& (GET_CODE (operands[2]) != REG
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|| REGNO(operands[0]) != REGNO (operands[2]))"
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@ -261,7 +261,7 @@ in the following sections.
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-mapcs-reentrant -mno-apcs-reentrant
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-msched-prolog -mno-sched-prolog
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-mlittle-endian -mbig-endian -mwords-little-endian
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-mshort-load-bytes -mno-short-load-bytes -mshort-load-words -mno-short-load-words
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-malignment-traps
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-msoft-float -mhard-float -mfpe
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-mthumb-interwork -mno-thumb-interwork
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-mcpu= -march= -mfpe=
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@ -4372,26 +4372,53 @@ option should only be used if you require compatibility with code for
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big-endian ARM processors generated by versions of the compiler prior to
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2.8.
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@item -malignment-traps
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@kindex -malignment-traps
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Generate code that will not trap if the MMU has alignment traps enabled.
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On ARM architectures prior to ARMv4, there were no instructions to
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access half-word objects stored in memory. However, when reading from
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memory a feature of the ARM architecture allows a word load to be used,
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even if the address is unaligned, and the processor core will rotate the
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data as it is being loaded. This option tells the compiler that such
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misaligned accesses will cause a MMU trap and that it should instead
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synthesise the access as a series of byte accesses. The compiler can
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still use word accesses to load half-word data if it knows that the
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address is aligned to a word boundary.
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This option is ignored when compiling for ARM architecture 4 or later,
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since these processors have instructions to directly access half-word
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objects in memory.
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@item -mno-alignment-traps
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@kindex -mno-alignment-traps
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Generate code that assumes that the MMU will not trap unaligned
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accesses. This produces better code when the target instruction set
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does not have half-word memory operations (implementations prior to
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ARMv4).
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Note that you cannot use this option to access unaligned word objects,
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since the processor will only fetch one 32-bit aligned object from
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memory.
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The default setting for most targets is -mno-alignment-traps, since
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this produces better code when there are no half-word memory
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instructions available.
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@item -mshort-load-bytes
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@kindex -mshort-load-bytes
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Do not try to load half-words (eg @samp{short}s) by loading a word from
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an unaligned address. For some targets the MMU is configured to trap
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unaligned loads; use this option to generate code that is safe in these
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environments.
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This is a depreciated alias for @samp{-malignment-traps}.
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@item -mno-short-load-bytes
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@kindex -mno-short-load-bytes
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Use unaligned word loads to load half-words (eg @samp{short}s). This
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option produces more efficient code, but the MMU is sometimes configured
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to trap these instructions.
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This is a depreciated alias for @samp{-mno-alignment-traps}.
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@item -mshort-load-words
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@kindex -mshort-load-words
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This is a synonym for @samp{-mno-short-load-bytes}.
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This is a depreciated alias for @samp{-mno-alignment-traps}.
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@item -mno-short-load-words
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@kindex -mno-short-load-words
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This is a synonym for @samp{-mshort-load-bytes}.
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This is a depreciated alias for @samp{-malignment-traps}.
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@item -mbsd
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@kindex -mbsd
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