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arc: Remove Rcw constraint
gcc/Changelog: * config/arc/arc.md (smaxsi3): Remove Rcw. (sminsi3): Likewise. (addsi3_mixed): Likewise. (add_f_2): Likewise. (subsi3_insn): Likewise. (sub_f): Likewise. (sub_n): Likewise. (bset): Likewise. (bxor): Likewise. (bclr): Likewise. (bset_insn): Likewise. (bxor_insn): Likewise. (bclr_insn): Likewise. (bmsk_insn): Likewise. (bicsi3_insn): Likewise. (xorsi3): Likewise. (negsi2): Likewise. (lshrsi3_insn): Likewise. (abssf2): Likewise. (negsf2): Likewise. * config/arc/constraints.md(Rcw): Remove it. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
This commit is contained in:
Claudiu Zissulescu
parent
af681e948f
commit
5ebbdf9c4e
@ -1991,22 +1991,22 @@ archs4x, archs4xd"
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;; Maximum and minimum insns
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(define_insn "smaxsi3"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcw, w, w")
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(smax:SI (match_operand:SI 1 "register_operand" "%0, c, c")
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(match_operand:SI 2 "nonmemory_operand" "cL,cL,Cal")))]
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[(set (match_operand:SI 0 "dest_reg_operand" "=r, r, r")
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(smax:SI (match_operand:SI 1 "register_operand" "%0, r, r")
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(match_operand:SI 2 "nonmemory_operand" "rL,rL,Cal")))]
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""
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"max%? %0,%1,%2"
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"max%?\\t%0,%1,%2"
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[(set_attr "type" "two_cycle_core")
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(set_attr "length" "4,4,8")
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(set_attr "predicable" "yes,no,no")]
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)
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(define_insn "sminsi3"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcw, w, w")
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(smin:SI (match_operand:SI 1 "register_operand" "%0, c, c")
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(match_operand:SI 2 "nonmemory_operand" "cL,cL,Cal")))]
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[(set (match_operand:SI 0 "dest_reg_operand" "=r, r, r")
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(smin:SI (match_operand:SI 1 "register_operand" "%0, r, r")
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(match_operand:SI 2 "nonmemory_operand" "rL,rL,Cal")))]
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""
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"min%? %0,%1,%2"
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"min%?\\t%0,%1,%2"
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[(set_attr "type" "two_cycle_core")
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(set_attr "length" "4,4,8")
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(set_attr "predicable" "yes,no,no")]
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@ -2028,10 +2028,10 @@ archs4x, archs4xd"
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; We avoid letting this pattern use LP_COUNT as a register by specifying
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; register class 'W' instead of 'w'.
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(define_insn_and_split "*addsi3_mixed"
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;; 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,Rcq, h,!*Rsd,Rcq,Rcb,Rcq, Rcqq,Rcqq,Rcw,Rcw, Rcw, W, W,W, W,Rcqq,Rcw, W")
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(plus:SI (match_operand:SI 1 "register_operand" "%0, c, 0, Rcqq, 0, 0,Rcb, Rcqq, 0, 0, c, 0, c, c,0, 0, 0, 0, c")
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(match_operand:SI 2 "nonmemory_operand" "cL, 0, Cm1, L,CL2,Csp,CM4,RcqqK, cO, cL, 0,cCca,cLCmL,Cca,I,C2a, Cal,Cal,Cal")))]
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;; 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,Rcq, h,!*Rsd,Rcq,Rcb,Rcq, Rcqq,Rcqq, r,r, r, W, W,W, W,Rcqq, r, W")
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(plus:SI (match_operand:SI 1 "register_operand" "%0, c, 0, Rcqq, 0, 0,Rcb, Rcqq, 0, 0,r, 0, c, c,0, 0, 0, 0, c")
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(match_operand:SI 2 "nonmemory_operand" "cL, 0, Cm1, L,CL2,Csp,CM4,RcqqK, cO,rL,0,rCca,cLCmL,Cca,I,C2a, Cal,Cal,Cal")))]
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""
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{
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arc_output_addsi (operands, arc_ccfsm_cond_exec_p (), true);
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@ -2792,13 +2792,13 @@ archs4x, archs4xd"
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(define_insn "*add_f_2"
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[(set (reg:CC_C CC_REG)
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(compare:CC_C
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(plus:SI (match_operand:SI 1 "register_operand" "c,0,c")
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(match_operand:SI 2 "nonmemory_operand" "cL,I,cCal"))
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(plus:SI (match_operand:SI 1 "register_operand" "r ,0,r")
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(match_operand:SI 2 "nonmemory_operand" "rL,I,rCal"))
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(match_dup 2)))
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(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w")
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(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
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(plus:SI (match_dup 1) (match_dup 2)))]
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""
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"add.f %0,%1,%2"
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"add.f\\t%0,%1,%2"
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[(set_attr "cond" "set")
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(set_attr "type" "compare")
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(set_attr "length" "4,4,8")])
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@ -2895,22 +2895,22 @@ archs4x, archs4xd"
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; the casesi expander might generate a sub of zero, so we have to recognize it.
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; combine should make such an insn go away.
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(define_insn_and_split "subsi3_insn"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcqq,Rcw,Rcw,w,w,w, w, w, w")
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(minus:SI (match_operand:SI 1 "nonmemory_operand" "0,Rcqq, 0, cL,c,L,I,Cal,Cal, c")
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(match_operand:SI 2 "nonmemory_operand" "Rcqq,Rcqq, c, 0,c,c,0, 0, c,Cal")))]
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcqq,r, r,r,r,r, r, r, r")
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(minus:SI (match_operand:SI 1 "nonmemory_operand" "0,Rcqq,0,rL,r,L,I,Cal,Cal, r")
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(match_operand:SI 2 "nonmemory_operand" "Rcqq,Rcqq,r, 0,r,r,0, 0, r,Cal")))]
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"register_operand (operands[1], SImode)
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|| register_operand (operands[2], SImode)"
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"@
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sub%? %0,%1,%2%&
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sub%? %0,%1,%2%&
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sub%? %0,%1,%2
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rsub%? %0,%2,%1
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sub %0,%1,%2
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rsub %0,%2,%1
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rsub %0,%2,%1
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rsub%? %0,%2,%1
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rsub %0,%2,%1
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sub %0,%1,%2"
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sub%?\\t%0,%1,%2%&
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sub%?\\t%0,%1,%2%&
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sub%?\\t%0,%1,%2
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rsub%?\\t%0,%2,%1
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sub\\t%0,%1,%2
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rsub\\t%0,%2,%1
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rsub\\t%0,%2,%1
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rsub%?\\t%0,%2,%1
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rsub\\t%0,%2,%1
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sub\\t%0,%1,%2"
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"reload_completed && get_attr_length (insn) == 8
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&& satisfies_constraint_I (operands[1])
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&& GET_CODE (PATTERN (insn)) != COND_EXEC"
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@ -2990,19 +2990,19 @@ archs4x, archs4xd"
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(define_insn "sub_f"
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[(set (reg:CC CC_REG)
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(compare:CC (match_operand:SI 1 "nonmemory_operand" " c,L,0,I,c,Cal")
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(match_operand:SI 2 "nonmemory_operand" "cL,c,I,0,Cal,c")))
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(set (match_operand:SI 0 "dest_reg_operand" "=w,w,Rcw,Rcw,w,w")
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(compare:CC (match_operand:SI 1 "nonmemory_operand" " r,L,0,I,r,Cal")
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(match_operand:SI 2 "nonmemory_operand" "rL,r,I,0,Cal,r")))
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(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r,r,r,r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"register_operand (operands[1], SImode)
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|| register_operand (operands[2], SImode)"
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"@
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sub.f %0,%1,%2
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rsub.f %0,%2,%1
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sub.f %0,%1,%2
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rsub.f %0,%2,%1
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sub.f %0,%1,%2
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sub.f %0,%1,%2"
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sub.f\\t%0,%1,%2
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rsub.f\\t%0,%2,%1
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sub.f\\t%0,%1,%2
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rsub.f\\t%0,%2,%1
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sub.f\\t%0,%1,%2
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sub.f\\t%0,%1,%2"
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[(set_attr "type" "compare")
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(set_attr "length" "4,4,4,4,8,8")])
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@ -3051,12 +3051,12 @@ archs4x, archs4xd"
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;; N.B. sub[123] has the operands of the MINUS in the opposite order from
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;; what synth_mult likes.
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(define_insn "*sub_n"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w")
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(minus:SI (match_operand:SI 1 "nonmemory_operand" "0,c,?Cal")
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(ashift:SI (match_operand:SI 2 "register_operand" "c,c,c")
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[(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
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(minus:SI (match_operand:SI 1 "nonmemory_operand" "0,r,?Cal")
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(ashift:SI (match_operand:SI 2 "register_operand" "r,r,r")
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(match_operand:SI 3 "_1_2_3_operand" ""))))]
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""
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"sub%c3%? %0,%1,%2"
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"sub%c3%?\\t%0,%1,%2"
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[(set_attr "type" "shift")
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(set_attr "length" "4,4,8")
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(set_attr "predicable" "yes,no,no")
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@ -3064,12 +3064,12 @@ archs4x, archs4xd"
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(set_attr "iscompact" "false")])
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(define_insn "*sub_n"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w")
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(minus:SI (match_operand:SI 1 "nonmemory_operand" "0,c,?Cal")
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(mult:SI (match_operand:SI 2 "register_operand" "c,c,c")
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[(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
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(minus:SI (match_operand:SI 1 "nonmemory_operand" "0,r,?Cal")
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(mult:SI (match_operand:SI 2 "register_operand" "r,r,r")
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(match_operand:SI 3 "_2_4_8_operand" ""))))]
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""
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"sub%z3%? %0,%1,%2"
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"sub%z3%?\\t%0,%1,%2"
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[(set_attr "type" "shift")
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(set_attr "length" "4,4,8")
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(set_attr "predicable" "yes,no,no")
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@ -3078,12 +3078,12 @@ archs4x, archs4xd"
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; ??? check if combine matches this.
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(define_insn "*bset"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w")
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[(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
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(ior:SI (ashift:SI (const_int 1)
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(match_operand:SI 1 "nonmemory_operand" "cL,cL,c"))
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(match_operand:SI 2 "nonmemory_operand" "0,c,Cal")))]
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(match_operand:SI 1 "nonmemory_operand" "rL,rL,r"))
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(match_operand:SI 2 "nonmemory_operand" "0,r,Cal")))]
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""
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"bset%? %0,%2,%1"
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"bset%?\\t%0,%2,%1"
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[(set_attr "length" "4,4,8")
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(set_attr "predicable" "yes,no,no")
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(set_attr "cond" "canuse,nocond,nocond")]
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@ -3091,12 +3091,12 @@ archs4x, archs4xd"
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; ??? check if combine matches this.
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(define_insn "*bxor"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w")
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[(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
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(xor:SI (ashift:SI (const_int 1)
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(match_operand:SI 1 "nonmemory_operand" "cL,cL,c"))
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(match_operand:SI 2 "nonmemory_operand" "0,c,Cal")))]
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(match_operand:SI 1 "nonmemory_operand" "rL,rL,r"))
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(match_operand:SI 2 "nonmemory_operand" "0,r,Cal")))]
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""
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"bxor%? %0,%2,%1"
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"bxor%?\\t%0,%2,%1"
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[(set_attr "length" "4,4,8")
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(set_attr "predicable" "yes,no,no")
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(set_attr "cond" "canuse,nocond,nocond")]
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@ -3104,12 +3104,12 @@ archs4x, archs4xd"
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; ??? check if combine matches this.
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(define_insn "*bclr"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w")
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[(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
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(and:SI (not:SI (ashift:SI (const_int 1)
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(match_operand:SI 1 "nonmemory_operand" "cL,cL,c")))
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(match_operand:SI 2 "nonmemory_operand" "0,c,Cal")))]
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(match_operand:SI 1 "nonmemory_operand" "rL,rL,r")))
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(match_operand:SI 2 "nonmemory_operand" "0,r,Cal")))]
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""
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"bclr%? %0,%2,%1"
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"bclr%?\\t%0,%2,%1"
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[(set_attr "length" "4,4,8")
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(set_attr "predicable" "yes,no,no")
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(set_attr "cond" "canuse,nocond,nocond")]
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@ -3121,15 +3121,15 @@ archs4x, archs4xd"
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; see also iorsi3 for use with constant bit number.
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(define_insn "*bset_insn"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w")
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(ior:SI (match_operand:SI 1 "nonmemory_operand" "0,c,Cal")
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[(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
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(ior:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal")
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(ashift:SI (const_int 1)
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(match_operand:SI 2 "nonmemory_operand" "cL,cL,c"))) ) ]
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(match_operand:SI 2 "nonmemory_operand" "rL,rL,r"))) ) ]
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""
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"@
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bset%? %0,%1,%2 ;;peep2, constr 1
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bset %0,%1,%2 ;;peep2, constr 2
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bset %0,%1,%2 ;;peep2, constr 3"
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bset%?\\t%0,%1,%2 ;;peep2, constr 1
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bset\\t%0,%1,%2 ;;peep2, constr 2
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bset\\t%0,%1,%2 ;;peep2, constr 3"
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[(set_attr "length" "4,4,8")
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(set_attr "predicable" "yes,no,no")
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(set_attr "cond" "canuse,nocond,nocond")]
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@ -3137,15 +3137,15 @@ archs4x, archs4xd"
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; see also xorsi3 for use with constant bit number.
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(define_insn "*bxor_insn"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w")
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(xor:SI (match_operand:SI 1 "nonmemory_operand" "0,c,Cal")
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[(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
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(xor:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal")
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(ashift:SI (const_int 1)
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(match_operand:SI 2 "nonmemory_operand" "cL,cL,c"))) ) ]
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(match_operand:SI 2 "nonmemory_operand" "rL,rL,r"))) ) ]
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""
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"@
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bxor%? %0,%1,%2
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bxor %0,%1,%2
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bxor %0,%1,%2"
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bxor%?\\t%0,%1,%2
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bxor\\t%0,%1,%2
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bxor\\t%0,%1,%2"
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[(set_attr "length" "4,4,8")
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(set_attr "predicable" "yes,no,no")
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(set_attr "cond" "canuse,nocond,nocond")]
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@ -3153,15 +3153,15 @@ archs4x, archs4xd"
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; see also andsi3 for use with constant bit number.
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(define_insn "*bclr_insn"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w")
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[(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
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(and:SI (not:SI (ashift:SI (const_int 1)
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(match_operand:SI 2 "nonmemory_operand" "cL,rL,r")))
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(match_operand:SI 1 "nonmemory_operand" "0,c,Cal")))]
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(match_operand:SI 2 "nonmemory_operand" "rL,rL,r")))
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(match_operand:SI 1 "nonmemory_operand" "0,r,Cal")))]
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""
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"@
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bclr%? %0,%1,%2
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bclr %0,%1,%2
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bclr %0,%1,%2"
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bclr%?\\t%0,%1,%2
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bclr\\t%0,%1,%2
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bclr\\t%0,%1,%2"
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[(set_attr "length" "4,4,8")
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(set_attr "predicable" "yes,no,no")
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(set_attr "cond" "canuse,nocond,nocond")]
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@ -3169,17 +3169,17 @@ archs4x, archs4xd"
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; see also andsi3 for use with constant bit number.
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(define_insn "*bmsk_insn"
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[(set (match_operand:SI 0 "dest_reg_operand" "=Rcw,w,w")
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(and:SI (match_operand:SI 1 "nonmemory_operand" "0,c,Cal")
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[(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
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(and:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal")
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(plus:SI (ashift:SI (const_int 1)
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(plus:SI (match_operand:SI 2 "nonmemory_operand" "rL,rL,r")
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(const_int 1)))
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(const_int -1))))]
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""
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"@
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bmsk%? %0,%1,%2
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bmsk %0,%1,%2
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bmsk %0,%1,%2"
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bmsk%?\\t%0,%1,%2
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bmsk\\t%0,%1,%2
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bmsk\\t%0,%1,%2"
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[(set_attr "length" "4,4,8")
|
||||
(set_attr "predicable" "yes,no,no")
|
||||
(set_attr "cond" "canuse,nocond,nocond")]
|
||||
@ -3282,18 +3282,18 @@ archs4x, archs4xd"
|
||||
|
||||
;;bic define_insn that allows limm to be the first operand
|
||||
(define_insn "*bicsi3_insn"
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcw,Rcw,Rcw,w,w,w")
|
||||
(and:SI (not:SI (match_operand:SI 1 "nonmemory_operand" "Rcqq,Lc,I,Cal,Lc,Cal,c"))
|
||||
(match_operand:SI 2 "nonmemory_operand" "0,0,0,0,c,c,Cal")))]
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,r,r,r,r,r,r")
|
||||
(and:SI (not:SI (match_operand:SI 1 "nonmemory_operand" "Rcqq,Lr,I,Cal,Lr,Cal,r"))
|
||||
(match_operand:SI 2 "nonmemory_operand" "0,0,0,0,r,r,Cal")))]
|
||||
""
|
||||
"@
|
||||
bic%? %0, %2, %1%& ;;constraint 0
|
||||
bic%? %0,%2,%1 ;;constraint 1
|
||||
bic %0,%2,%1 ;;constraint 2, FIXME: will it ever get generated ???
|
||||
bic%? %0,%2,%1 ;;constraint 3, FIXME: will it ever get generated ???
|
||||
bic %0,%2,%1 ;;constraint 4
|
||||
bic %0,%2,%1 ;;constraint 5, FIXME: will it ever get generated ???
|
||||
bic %0,%2,%1 ;;constraint 6"
|
||||
bic%?\\t%0, %2, %1%& ;;constraint 0
|
||||
bic%?\\t%0,%2,%1 ;;constraint 1
|
||||
bic\\t%0,%2,%1 ;;constraint 2, FIXME: will it ever get generated ???
|
||||
bic%?\\t%0,%2,%1 ;;constraint 3, FIXME: will it ever get generated ???
|
||||
bic\\t%0,%2,%1 ;;constraint 4
|
||||
bic\\t%0,%2,%1 ;;constraint 5, FIXME: will it ever get generated ???
|
||||
bic\\t%0,%2,%1 ;;constraint 6"
|
||||
[(set_attr "length" "*,4,4,8,4,8,8")
|
||||
(set_attr "iscompact" "maybe, false, false, false, false, false, false")
|
||||
(set_attr "predicable" "no,yes,no,yes,no,no,no")
|
||||
@ -3334,19 +3334,19 @@ archs4x, archs4xd"
|
||||
(set_attr "cond" "canuse,canuse,canuse,canuse,canuse,canuse,canuse_limm,nocond,nocond,canuse_limm,nocond,canuse,nocond")])
|
||||
|
||||
(define_insn "xorsi3"
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcq,Rcw,Rcw,Rcw,Rcw, w, w,w, w, w")
|
||||
(xor:SI (match_operand:SI 1 "register_operand" "%0, Rcq, 0, c, 0, 0, c, c,0, 0, c")
|
||||
(match_operand:SI 2 "nonmemory_operand" " Rcqq, 0, cL, 0,C0p, I,cL,C0p,I,Cal,Cal")))]
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcq, r,r, r,r, r, r,r, r, r")
|
||||
(xor:SI (match_operand:SI 1 "register_operand" "%0, Rcq, 0,r, 0,0, r, r,0, 0, r")
|
||||
(match_operand:SI 2 "nonmemory_operand" " Rcqq, 0,rL,0,C0p,I,rL,C0p,I,Cal,Cal")))]
|
||||
""
|
||||
"*
|
||||
switch (which_alternative)
|
||||
{
|
||||
case 0: case 2: case 5: case 6: case 8: case 9: case 10:
|
||||
return \"xor%? %0,%1,%2%&\";
|
||||
return \"xor%?\\t%0,%1,%2%&\";
|
||||
case 1: case 3:
|
||||
return \"xor%? %0,%2,%1%&\";
|
||||
return \"xor%?\\t%0,%2,%1%&\";
|
||||
case 4: case 7:
|
||||
return \"bxor%? %0,%1,%z2\";
|
||||
return \"bxor%?\\t%0,%1,%z2\";
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}
|
||||
@ -3358,10 +3358,10 @@ archs4x, archs4xd"
|
||||
(set_attr "cond" "canuse,canuse,canuse,canuse,canuse,canuse_limm,nocond,nocond,canuse_limm,canuse,nocond")])
|
||||
|
||||
(define_insn "negsi2"
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcqq,Rcw,w")
|
||||
(neg:SI (match_operand:SI 1 "register_operand" "0,Rcqq,0,c")))]
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcqq,r,r")
|
||||
(neg:SI (match_operand:SI 1 "register_operand" "0,Rcqq,0,r")))]
|
||||
""
|
||||
"neg%? %0,%1%&"
|
||||
"neg%?\\t%0,%1%&"
|
||||
[(set_attr "type" "unary")
|
||||
(set_attr "iscompact" "maybe,true,false,false")
|
||||
(set_attr "predicable" "no,no,yes,no")])
|
||||
@ -3498,14 +3498,14 @@ archs4x, archs4xd"
|
||||
(set_attr "cond" "canuse,nocond,canuse,canuse,nocond,nocond")])
|
||||
|
||||
(define_insn "*lshrsi3_insn"
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w")
|
||||
(lshiftrt:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCal")
|
||||
(match_operand:SI 2 "nonmemory_operand" "N, N,RcqqM, cL,cL,cCal")))]
|
||||
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq, r, r, r")
|
||||
(lshiftrt:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, r,rCal")
|
||||
(match_operand:SI 2 "nonmemory_operand" "N, N,RcqqM,rL,rL,rCal")))]
|
||||
"TARGET_BARREL_SHIFTER
|
||||
&& (register_operand (operands[1], SImode)
|
||||
|| register_operand (operands[2], SImode))"
|
||||
"*return (which_alternative <= 1 && !arc_ccfsm_cond_exec_p ()
|
||||
? \"lsr%? %0,%1%&\" : \"lsr%? %0,%1,%2%&\");"
|
||||
? \"lsr%?\\t%0,%1%&\" : \"lsr%?\\t%0,%1,%2%&\");"
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "iscompact" "maybe,maybe,maybe,false,false,false")
|
||||
(set_attr "predicable" "no,no,no,yes,no,no")
|
||||
@ -5153,20 +5153,20 @@ archs4x, archs4xd"
|
||||
(set_attr "predicable" "yes")])
|
||||
|
||||
(define_insn "abssf2"
|
||||
[(set (match_operand:SF 0 "dest_reg_operand" "=Rcq#q,Rcw,w")
|
||||
(abs:SF (match_operand:SF 1 "register_operand" "0, 0,c")))]
|
||||
[(set (match_operand:SF 0 "dest_reg_operand" "=Rcq#q,r,r")
|
||||
(abs:SF (match_operand:SF 1 "register_operand" "0,0,r")))]
|
||||
""
|
||||
"bclr%? %0,%1,31%&"
|
||||
"bclr%?\\t%0,%1,31%&"
|
||||
[(set_attr "type" "unary")
|
||||
(set_attr "iscompact" "maybe,false,false")
|
||||
(set_attr "length" "2,4,4")
|
||||
(set_attr "predicable" "no,yes,no")])
|
||||
|
||||
(define_insn "negsf2"
|
||||
[(set (match_operand:SF 0 "dest_reg_operand" "=Rcw,w")
|
||||
(neg:SF (match_operand:SF 1 "register_operand" "0,c")))]
|
||||
[(set (match_operand:SF 0 "dest_reg_operand" "=r,r")
|
||||
(neg:SF (match_operand:SF 1 "register_operand" "0,r")))]
|
||||
""
|
||||
"bxor%? %0,%1,31"
|
||||
"bxor%?\\t%0,%1,31"
|
||||
[(set_attr "type" "unary")
|
||||
(set_attr "predicable" "yes,no")])
|
||||
|
||||
|
||||
@ -452,20 +452,6 @@
|
||||
&& !arc_ccfsm_cond_exec_p ()
|
||||
&& IN_RANGE (REGNO (op) ^ 4, 4, 11)")))
|
||||
|
||||
; If we need a reload, we generally want to steer reload to use three-address
|
||||
; alternatives in preference of two-address alternatives, unless the
|
||||
; three-address alternative introduces a LIMM that is unnecessary for the
|
||||
; two-address alternative.
|
||||
(define_constraint "Rcw"
|
||||
"@internal
|
||||
Cryptic w - for use in early alternatives with matching constraint"
|
||||
(and (match_code "reg")
|
||||
(match_test
|
||||
"TARGET_Rcw
|
||||
&& REGNO (op) < FIRST_PSEUDO_REGISTER
|
||||
&& TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS],
|
||||
REGNO (op))")))
|
||||
|
||||
(define_constraint "Rcb"
|
||||
"@internal
|
||||
Stack Pointer register @code{r28} - do not reload into its class"
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user