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alpha.md (zero_extendqihi2, [...]): Use and 255 instead of zapnot 1, since it schedules better.

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* alpha.md (zero_extendqihi2, zero_extendqisi2, zero_extendqidi2):
        Use and 255 instead of zapnot 1, since it schedules better.

From-SVN: r17103
This commit is contained in:
Richard Henderson 1997-12-15 09:55:10 -08:00 committed by Richard Henderson
parent 395928138c
commit 5e21ac7a62
2 changed files with 15 additions and 10 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
Mon Dec 15 09:44:39 1997 Richard Henderson <rth@cygnus.com>
* alpha.md (zero_extendqihi2, zero_extendqisi2, zero_extendqidi2):
Use and 255 instead of zapnot 1, since it schedules better.
Mon Dec 15 08:48:24 1997 Jeffrey A Law (law@cygnus.com) Mon Dec 15 08:48:24 1997 Jeffrey A Law (law@cygnus.com)
* stmt.c (expand_asm_operands): If an ASM has no outputs, then treat * stmt.c (expand_asm_operands): If an ASM has no outputs, then treat

20
gcc/config/alpha/alpha.md
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@ -811,24 +811,24 @@
[(set (match_operand:HI 0 "register_operand" "=r") [(set (match_operand:HI 0 "register_operand" "=r")
(zero_extend:HI (match_operand:QI 1 "register_operand" "r")))] (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
"" ""
"zapnot %1,1,%0" "and %1,255,%0"
[(set_attr "type" "shift")]) [(set_attr "type" "ilog")])
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
"TARGET_BWX" "TARGET_BWX"
"@ "@
zapnot %1,1,%0 and %1,255,%0
ldbu %0,%1" ldbu %0,%1"
[(set_attr "type" "shift,ld")]) [(set_attr "type" "ilog,ld")])
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI (match_operand:QI 1 "register_operand" "r")))] (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
"! TARGET_BWX" "! TARGET_BWX"
"zapnot %1,1,%0" "and %1,255,%0"
[(set_attr "type" "shift")]) [(set_attr "type" "ilog")])
(define_expand "zero_extendqisi2" (define_expand "zero_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
@ -841,16 +841,16 @@
(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
"TARGET_BWX" "TARGET_BWX"
"@ "@
zapnot %1,1,%0 and %1,255,%0
ldbu %0,%1" ldbu %0,%1"
[(set_attr "type" "shift,ld")]) [(set_attr "type" "ilog,ld")])
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (match_operand:QI 1 "register_operand" "r")))] (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
"! TARGET_BWX" "! TARGET_BWX"
"zapnot %1,1,%0" "and %1,255,%0"
[(set_attr "type" "shift")]) [(set_attr "type" "ilog")])
(define_expand "zero_extendqidi2" (define_expand "zero_extendqidi2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")