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s390-modes.def (CCL3mode): New machine mode.
* config/s390/s390-modes.def (CCL3mode): New machine mode.
* config/s390/s390.c (s390_match_ccmode_set): Support CCL3mode.
(s390_alc_comparison, s390_slb_comparison): Likewise.
(s390_branch_condition_mask): Likewise.
* config/s390/s390.md ("*subdi3_cc2", "*subdi3_cconly2"): New.
("*subsi3_cc2", "*subsi3_cconly2"): New.
* config/s390/s390.h (PREDICATE_CODE): Accept SIGN_EXTEND and
ZERO_EXTEND for s390_alc_comparison and s390_slb_comparison.
* config/s390/s390.c (s390_alc_comparison, s390_slb_comparison):
Handle SIGN_EXTEND and ZERO_EXTEND.
* config/s390/s390-protos.h (s390_expand_addcc): New prototype.
* config/s390/s390.c (s390_expand_addcc): New function.
* config/s390/s390.md ("adddicc", "addsicc"): New expanders.
("*sconddi", "*scondsi", "*sconddi_neg", "*scondsi_neg"): New insns.
("sltu", "sgtu", "sleu", "sgeu"): New expanders.
From-SVN: r83287
This commit is contained in:
Ulrich Weigand
Ulrich Weigand
parent
ac5347368c
commit
5d880bd24b
@ -1,3 +1,23 @@
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2004-06-17 Ulrich Weigand <uweigand@de.ibm.com>
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* config/s390/s390-modes.def (CCL3mode): New machine mode.
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* config/s390/s390.c (s390_match_ccmode_set): Support CCL3mode.
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(s390_alc_comparison, s390_slb_comparison): Likewise.
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(s390_branch_condition_mask): Likewise.
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* config/s390/s390.md ("*subdi3_cc2", "*subdi3_cconly2"): New.
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("*subsi3_cc2", "*subsi3_cconly2"): New.
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* config/s390/s390.h (PREDICATE_CODE): Accept SIGN_EXTEND and
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ZERO_EXTEND for s390_alc_comparison and s390_slb_comparison.
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* config/s390/s390.c (s390_alc_comparison, s390_slb_comparison):
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Handle SIGN_EXTEND and ZERO_EXTEND.
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* config/s390/s390-protos.h (s390_expand_addcc): New prototype.
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* config/s390/s390.c (s390_expand_addcc): New function.
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* config/s390/s390.md ("adddicc", "addsicc"): New expanders.
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("*sconddi", "*scondsi", "*sconddi_neg", "*scondsi_neg"): New insns.
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("sltu", "sgtu", "sleu", "sgeu"): New expanders.
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2004-06-17 Ben Elliston <bje@au.ibm.com>
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* tree-alias-common.c: Add whitespace.
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@ -32,6 +32,7 @@ CC_MODE (CCAN);
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CC_MODE (CCL);
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CC_MODE (CCL1);
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CC_MODE (CCL2);
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CC_MODE (CCL3);
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CC_MODE (CCU);
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CC_MODE (CCUR);
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CC_MODE (CCS);
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@ -76,6 +76,7 @@ extern void s390_load_address (rtx, rtx);
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extern void s390_expand_movstr (rtx, rtx, rtx);
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extern void s390_expand_clrstr (rtx, rtx);
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extern void s390_expand_cmpmem (rtx, rtx, rtx, rtx);
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extern bool s390_expand_addcc (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
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extern rtx s390_return_addr_rtx (int, rtx);
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extern rtx s390_emit_call (rtx, rtx, rtx, rtx);
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@ -282,6 +282,7 @@ s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
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case CCLmode:
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case CCL1mode:
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case CCL2mode:
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case CCL3mode:
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case CCT1mode:
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case CCT2mode:
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case CCT3mode:
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@ -477,6 +478,9 @@ s390_alc_comparison (rtx op, enum machine_mode mode)
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if (mode != VOIDmode && mode != GET_MODE (op))
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return 0;
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while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
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op = XEXP (op, 0);
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if (!COMPARISON_P (op))
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return 0;
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@ -493,6 +497,9 @@ s390_alc_comparison (rtx op, enum machine_mode mode)
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case CCL2mode:
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return GET_CODE (op) == LEU;
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case CCL3mode:
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return GET_CODE (op) == GEU;
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case CCUmode:
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return GET_CODE (op) == GTU;
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@ -519,6 +526,9 @@ s390_slb_comparison (rtx op, enum machine_mode mode)
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if (mode != VOIDmode && mode != GET_MODE (op))
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return 0;
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while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
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op = XEXP (op, 0);
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if (!COMPARISON_P (op))
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return 0;
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@ -535,6 +545,9 @@ s390_slb_comparison (rtx op, enum machine_mode mode)
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case CCL2mode:
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return GET_CODE (op) == GTU;
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case CCL3mode:
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return GET_CODE (op) == LTU;
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case CCUmode:
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return GET_CODE (op) == LEU;
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@ -640,6 +653,19 @@ s390_branch_condition_mask (rtx code)
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}
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break;
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case CCL3mode:
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switch (GET_CODE (code))
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{
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case EQ: return CC0 | CC2;
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case NE: return CC1 | CC3;
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case LTU: return CC1;
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case GTU: return CC3;
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case LEU: return CC1 | CC2;
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case GEU: return CC2 | CC3;
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default:
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abort ();
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}
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case CCUmode:
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switch (GET_CODE (code))
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{
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@ -3194,6 +3220,174 @@ s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
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#endif
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}
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/* Expand conditional increment or decrement using alc/slb instructions.
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Should generate code setting DST to either SRC or SRC + INCREMENT,
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depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
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Returns true if successful, false otherwise. */
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bool
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s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
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rtx dst, rtx src, rtx increment)
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{
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enum machine_mode cmp_mode;
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enum machine_mode cc_mode;
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rtx op_res;
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rtx insn;
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rtvec p;
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if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
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&& (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
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cmp_mode = SImode;
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else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
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&& (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
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cmp_mode = DImode;
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else
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return false;
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/* Try ADD LOGICAL WITH CARRY. */
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if (increment == const1_rtx)
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{
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/* Determine CC mode to use. */
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if (cmp_code == EQ || cmp_code == NE)
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{
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if (cmp_op1 != const0_rtx)
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{
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cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
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NULL_RTX, 0, OPTAB_WIDEN);
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cmp_op1 = const0_rtx;
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}
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cmp_code = cmp_code == EQ ? LEU : GTU;
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}
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if (cmp_code == LTU || cmp_code == LEU)
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{
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rtx tem = cmp_op0;
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cmp_op0 = cmp_op1;
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cmp_op1 = tem;
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cmp_code = swap_condition (cmp_code);
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}
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switch (cmp_code)
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{
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case GTU:
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cc_mode = CCUmode;
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break;
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case GEU:
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cc_mode = CCL3mode;
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break;
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default:
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return false;
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}
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/* Emit comparison instruction pattern. */
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if (!register_operand (cmp_op0, cmp_mode))
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cmp_op0 = force_reg (cmp_mode, cmp_op0);
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insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
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gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
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/* We use insn_invalid_p here to add clobbers if required. */
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if (insn_invalid_p (emit_insn (insn)))
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abort ();
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/* Emit ALC instruction pattern. */
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op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
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gen_rtx_REG (cc_mode, CC_REGNUM),
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const0_rtx);
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if (src != const0_rtx)
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{
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if (!register_operand (src, GET_MODE (dst)))
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src = force_reg (GET_MODE (dst), src);
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src = gen_rtx_PLUS (GET_MODE (dst), src, const0_rtx);
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op_res = gen_rtx_PLUS (GET_MODE (dst), src, op_res);
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}
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p = rtvec_alloc (2);
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RTVEC_ELT (p, 0) =
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gen_rtx_SET (VOIDmode, dst, op_res);
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RTVEC_ELT (p, 1) =
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
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emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
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return true;
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}
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/* Try SUBTRACT LOGICAL WITH BORROW. */
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if (increment == constm1_rtx)
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{
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/* Determine CC mode to use. */
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if (cmp_code == EQ || cmp_code == NE)
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{
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if (cmp_op1 != const0_rtx)
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{
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cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
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NULL_RTX, 0, OPTAB_WIDEN);
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cmp_op1 = const0_rtx;
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}
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cmp_code = cmp_code == EQ ? LEU : GTU;
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}
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if (cmp_code == GTU || cmp_code == GEU)
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{
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rtx tem = cmp_op0;
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cmp_op0 = cmp_op1;
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cmp_op1 = tem;
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cmp_code = swap_condition (cmp_code);
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}
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switch (cmp_code)
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{
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case LEU:
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cc_mode = CCUmode;
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break;
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case LTU:
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cc_mode = CCL3mode;
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break;
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default:
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return false;
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}
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/* Emit comparison instruction pattern. */
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if (!register_operand (cmp_op0, cmp_mode))
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cmp_op0 = force_reg (cmp_mode, cmp_op0);
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insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
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gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
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/* We use insn_invalid_p here to add clobbers if required. */
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if (insn_invalid_p (emit_insn (insn)))
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abort ();
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/* Emit SLB instruction pattern. */
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if (!register_operand (src, GET_MODE (dst)))
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src = force_reg (GET_MODE (dst), src);
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op_res = gen_rtx_MINUS (GET_MODE (dst),
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gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
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gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
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gen_rtx_REG (cc_mode, CC_REGNUM),
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const0_rtx));
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p = rtvec_alloc (2);
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RTVEC_ELT (p, 0) =
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gen_rtx_SET (VOIDmode, dst, op_res);
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RTVEC_ELT (p, 1) =
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
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emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
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return true;
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}
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return false;
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}
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/* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
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We need to emit DTP-relative relocations. */
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@ -990,8 +990,10 @@ do { \
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{"consttable_operand", { SYMBOL_REF, LABEL_REF, CONST, \
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CONST_INT, CONST_DOUBLE }}, \
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{"s390_plus_operand", { PLUS }}, \
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{"s390_alc_comparison", { LTU, GTU, LEU, GEU }}, \
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{"s390_slb_comparison", { LTU, GTU, LEU, GEU }},
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{"s390_alc_comparison", { ZERO_EXTEND, SIGN_EXTEND, \
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LTU, GTU, LEU, GEU }}, \
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{"s390_slb_comparison", { ZERO_EXTEND, SIGN_EXTEND, \
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LTU, GTU, LEU, GEU }},
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/* Specify the machine mode that this machine uses for the index in the
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tablejump instruction. */
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@ -3976,6 +3976,18 @@
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slg\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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(define_insn "*subdi3_cc2"
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[(set (reg 33)
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(compare (match_operand:DI 1 "register_operand" "0,0")
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(match_operand:DI 2 "general_operand" "d,m")))
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(set (match_operand:DI 0 "register_operand" "=d,d")
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(minus:DI (match_dup 1) (match_dup 2)))]
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"s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
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"@
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slgr\t%0,%2
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slg\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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(define_insn "*subdi3_cconly"
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[(set (reg 33)
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(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
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@ -3988,6 +4000,17 @@
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slg\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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(define_insn "*subdi3_cconly2"
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[(set (reg 33)
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(compare (match_operand:DI 1 "register_operand" "0,0")
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(match_operand:DI 2 "general_operand" "d,m")))
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(clobber (match_scratch:DI 0 "=d,d"))]
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"s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
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"@
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slgr\t%0,%2
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slg\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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(define_insn "*subdi3_64"
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[(set (match_operand:DI 0 "register_operand" "=d,d")
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(minus:DI (match_operand:DI 1 "register_operand" "0,0")
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@ -4111,6 +4134,19 @@
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sly\t%0,%2"
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[(set_attr "op_type" "RR,RX,RXY")])
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(define_insn "*subsi3_cc2"
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[(set (reg 33)
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(compare (match_operand:SI 1 "register_operand" "0,0,0")
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(match_operand:SI 2 "general_operand" "d,R,T")))
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(set (match_operand:SI 0 "register_operand" "=d,d,d")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"s390_match_ccmode (insn, CCL3mode)"
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"@
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slr\t%0,%2
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sl\t%0,%2
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sly\t%0,%2"
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[(set_attr "op_type" "RR,RX,RXY")])
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(define_insn "*subsi3_cconly"
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[(set (reg 33)
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(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
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@ -4124,6 +4160,18 @@
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sly\t%0,%2"
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[(set_attr "op_type" "RR,RX,RXY")])
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(define_insn "*subsi3_cconly2"
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[(set (reg 33)
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(compare (match_operand:SI 1 "register_operand" "0,0,0")
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(match_operand:SI 2 "general_operand" "d,R,T")))
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(clobber (match_scratch:SI 0 "=d,d,d"))]
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"s390_match_ccmode (insn, CCL3mode)"
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"@
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slr\t%0,%2
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sl\t%0,%2
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sly\t%0,%2"
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[(set_attr "op_type" "RR,RX,RXY")])
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(define_insn "*subsi3_sign"
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[(set (match_operand:SI 0 "register_operand" "=d,d")
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(minus:SI (match_operand:SI 1 "register_operand" "0,0")
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@ -4339,6 +4387,17 @@
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slbg\\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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(define_expand "adddicc"
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[(match_operand:DI 0 "register_operand" "")
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(match_operand 1 "comparison_operator" "")
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(match_operand:DI 2 "register_operand" "")
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(match_operand:DI 3 "const_int_operand" "")]
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"TARGET_64BIT"
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"if (!s390_expand_addcc (GET_CODE (operands[1]),
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s390_compare_op0, s390_compare_op1,
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operands[0], operands[2],
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operands[3])) FAIL; DONE;")
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;
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; addsicc instruction pattern(s).
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;
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@ -4397,6 +4456,111 @@
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slb\\t%0,%2"
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[(set_attr "op_type" "RRE,RXY")])
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(define_expand "addsicc"
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[(match_operand:SI 0 "register_operand" "")
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(match_operand 1 "comparison_operator" "")
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(match_operand:SI 2 "register_operand" "")
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(match_operand:SI 3 "const_int_operand" "")]
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||||
"TARGET_CPU_ZARCH"
|
||||
"if (!s390_expand_addcc (GET_CODE (operands[1]),
|
||||
s390_compare_op0, s390_compare_op1,
|
||||
operands[0], operands[2],
|
||||
operands[3])) FAIL; DONE;")
|
||||
|
||||
;
|
||||
; scond instruction pattern(s).
|
||||
;
|
||||
|
||||
(define_insn_and_split "*sconddi"
|
||||
[(set (match_operand:DI 0 "register_operand" "=&d")
|
||||
(match_operand:DI 1 "s390_alc_comparison" ""))
|
||||
(clobber (reg:CC 33))]
|
||||
"TARGET_64BIT"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(set (match_dup 0) (const_int 0))
|
||||
(parallel
|
||||
[(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0))
|
||||
(match_dup 1)))
|
||||
(clobber (reg:CC 33))])]
|
||||
""
|
||||
[(set_attr "op_type" "NN")])
|
||||
|
||||
(define_insn_and_split "*scondsi"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&d")
|
||||
(match_operand:SI 1 "s390_alc_comparison" ""))
|
||||
(clobber (reg:CC 33))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(set (match_dup 0) (const_int 0))
|
||||
(parallel
|
||||
[(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0))
|
||||
(match_dup 1)))
|
||||
(clobber (reg:CC 33))])]
|
||||
""
|
||||
[(set_attr "op_type" "NN")])
|
||||
|
||||
(define_insn_and_split "*sconddi_neg"
|
||||
[(set (match_operand:DI 0 "register_operand" "=&d")
|
||||
(match_operand:DI 1 "s390_slb_comparison" ""))
|
||||
(clobber (reg:CC 33))]
|
||||
"TARGET_64BIT"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(set (match_dup 0) (const_int 0))
|
||||
(parallel
|
||||
[(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0))
|
||||
(match_dup 1)))
|
||||
(clobber (reg:CC 33))])
|
||||
(parallel
|
||||
[(set (match_dup 0) (neg:DI (match_dup 0)))
|
||||
(clobber (reg:CC 33))])]
|
||||
""
|
||||
[(set_attr "op_type" "NN")])
|
||||
|
||||
(define_insn_and_split "*scondsi_neg"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&d")
|
||||
(match_operand:SI 1 "s390_slb_comparison" ""))
|
||||
(clobber (reg:CC 33))]
|
||||
"TARGET_CPU_ZARCH"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(set (match_dup 0) (const_int 0))
|
||||
(parallel
|
||||
[(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0))
|
||||
(match_dup 1)))
|
||||
(clobber (reg:CC 33))])
|
||||
(parallel
|
||||
[(set (match_dup 0) (neg:SI (match_dup 0)))
|
||||
(clobber (reg:CC 33))])]
|
||||
""
|
||||
[(set_attr "op_type" "NN")])
|
||||
|
||||
(define_expand "sltu"
|
||||
[(match_operand:SI 0 "register_operand" "")]
|
||||
"TARGET_CPU_ZARCH"
|
||||
"if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1,
|
||||
operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
|
||||
|
||||
(define_expand "sgtu"
|
||||
[(match_operand:SI 0 "register_operand" "")]
|
||||
"TARGET_CPU_ZARCH"
|
||||
"if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1,
|
||||
operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
|
||||
|
||||
(define_expand "sleu"
|
||||
[(match_operand:SI 0 "register_operand" "")]
|
||||
"TARGET_CPU_ZARCH"
|
||||
"if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1,
|
||||
operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
|
||||
|
||||
(define_expand "sgeu"
|
||||
[(match_operand:SI 0 "register_operand" "")]
|
||||
"TARGET_CPU_ZARCH"
|
||||
"if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1,
|
||||
operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
|
||||
|
||||
|
||||
;;
|
||||
;;- Multiply instructions.
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user