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invoke.texi (NS32K Options): Document -mieee-compare option
* doc/invoke.texi (NS32K Options): Document -mieee-compare option
* config/ns32k/ns32k.md (addsi3, *frame_addr, *stack_addr): merge
into addsi3 using register class "x" and "y".
* config/ns32k/ns32k.md (*madddf, *maddsf, *msubdf, *msubsf):
"earlyclobber" constraint modifier for some alternative.
* config/ns32k/ns32k.md (tstdf, tstsf, cmpdf, cmpsf, blt, ble)
(*ble, *blt): Flag to indicate bCOND and sCOND should check for
unordered.
config/ns32k/ns32k.h (CC_UNORD): define corresponding mask.
* config/ns32k/ns32k.h (TARGET_IEEE_COMPARE, MASK_IEEE_COMPARE)
(TARGET_SWITCHES): Add -mieee-compare option.
(OVERRIDE_OPTIONS): 32332 is a subset of
32532. Don't use IEEE_COMPARE -funsafe-math-optimizations.
(TARGET_SWITCHES): Fix description of bitfield option.
* config/ns32k/netbsd.h (TARGET_DEFAULT): Add
-mieee-compare option. Remove 32332 flag.
From-SVN: r55489
This commit is contained in:
Ian Dall
Richard Henderson
parent
5da4f54878
commit
5d7c281902
@ -1,15 +1,38 @@
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2002-07-16 Ian Dall <ian@sibyl.beware.dropbear.id.au>
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* doc/invoke.texi (NS32K Options): Document -mieee-compare option
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* config/ns32k/ns32k.md (addsi3, *frame_addr, *stack_addr): merge
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into addsi3 using register class "x" and "y".
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* config/ns32k/ns32k.md (*madddf, *maddsf, *msubdf, *msubsf):
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"earlyclobber" constraint modifier for some alternative.
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* config/ns32k/ns32k.md (tstdf, tstsf, cmpdf, cmpsf, blt, ble)
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(*ble, *blt): Flag to indicate bCOND and sCOND should check for
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unordered.
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config/ns32k/ns32k.h (CC_UNORD): define corresponding mask.
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* config/ns32k/ns32k.h (TARGET_IEEE_COMPARE, MASK_IEEE_COMPARE)
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(TARGET_SWITCHES): Add -mieee-compare option.
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(OVERRIDE_OPTIONS): 32332 is a subset of
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32532. Don't use IEEE_COMPARE -funsafe-math-optimizations.
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(TARGET_SWITCHES): Fix description of bitfield option.
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* config/ns32k/netbsd.h (TARGET_DEFAULT): Add
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-mieee-compare option. Remove 32332 flag.
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2002-07-16 Steve Ellcey <sje@cup.hp.com>
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* gcc/explow.c (convert_memory_address): Remove special handling
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* explow.c (convert_memory_address): Remove special handling
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when POINTERS_EXTEND_UNSIGNED < 0.
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* gcc/config/ia64.md (movsi_symbolic): New instruction for ILP32
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mode.
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* config/ia64.md (movsi_symbolic): New instruction for ILP32 mode.
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(movedi_symbolic): Fix typo.
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(load_fptr): Remove mode restriction so it works for SI and DI.
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(load_fptr_internal1): Ditto.
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(load_gprel): Ditto.
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(load_symptr_internal1): Ditto.
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(call_pic): Ditto.
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* gcc/config/ia64.c (call_operand): Modify mode check.
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* config/ia64.c (call_operand): Modify mode check.
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(ia64_expand_load_address): Handle DI and SI addresses and symbols.
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(ia64_expand_move): Ditto.
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(ia64_assemble_integer): Handle SImode function pointers.
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@ -34,9 +34,10 @@ Boston, MA 02111-1307, USA. */
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FPU is 32381;
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Use multiply-add instructions */
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#undef TARGET_DEFAULT
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#define TARGET_DEFAULT \
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(MASK_32532|MASK_32332 | MASK_NO_SB | MASK_NO_BITFIELD | \
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MASK_32081|MASK_32381 | MASK_MULT_ADD)
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(MASK_32532 | MASK_NO_SB | MASK_NO_BITFIELD | \
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MASK_32381 | MASK_IEEE_COMPARE | MASK_MULT_ADD)
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/* 32-bit alignment for efficiency */
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@ -82,6 +82,7 @@ Boston, MA 02111-1307, USA. */
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extern int target_flags;
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/* Masks for target_flags */
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#define MASK_32081 1
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#define MASK_RTD 2
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#define MASK_REGPARM 4
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@ -93,6 +94,7 @@ extern int target_flags;
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#define MASK_32381 256
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#define MASK_MULT_ADD 512
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#define MASK_SRC 1024
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#define MASK_IEEE_COMPARE 2048
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/* Macros used in the machine description to test the flags. */
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@ -121,17 +123,19 @@ extern int target_flags;
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/* Ok to use the static base register (and presume it's 0) */
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#define TARGET_SB ((target_flags & MASK_NO_SB) == 0)
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#define TARGET_HIMEM (target_flags & MASK_HIMEM)
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/* Compile using bitfield insns. */
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#define TARGET_BITFIELD ((target_flags & MASK_NO_BITFIELD) == 0)
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#define TARGET_IEEE_FP (target_flags & MASK_IEEE_COMPARE)
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/* Macro to define tables used to set the flags.
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This is a list in braces of pairs in braces,
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each pair being { "NAME", VALUE }
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where VALUE is the bits to set or minus the bits to clear.
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An empty string NAME is used to identify the default VALUE. */
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#define TARGET_SWITCHES \
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{ { "32081", MASK_32081, N_("Use hardware fp")}, \
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{ "soft-float", -(MASK_32081|MASK_32381), \
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@ -148,17 +152,21 @@ extern int target_flags;
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N_("Register sb is zero. Use for absolute addressing")}, \
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{ "nosb", MASK_NO_SB, N_("Do not use register sb")}, \
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{ "bitfield", -MASK_NO_BITFIELD, \
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N_("Use bit-field instructions")}, \
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{ "nobitfield", MASK_NO_BITFIELD, \
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N_("Do not use bit-field instructions")}, \
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{ "nobitfield", MASK_NO_BITFIELD, N_("Use bit-field instructions")},\
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{ "himem", MASK_HIMEM, N_("Generate code for high memory")}, \
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{ "nohimem", -MASK_HIMEM, N_("Generate code for low memory")}, \
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{ "32381", MASK_32381, N_("32381 fpu")}, \
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{ "mult-add", MASK_MULT_ADD, \
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N_("Use multiply-accumulate fp instructions")}, \
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{ "nomult-add", -MASK_MULT_ADD, \
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N_("Do not use multiply-accumulate fp instructions") }, \
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N_("Do not use multiply-accumulate fp instructions") }, \
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{ "src", MASK_SRC, N_("\"Small register classes\" kludge")}, \
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{ "nosrc", -MASK_SRC, N_("No \"Small register classes\" kludge")}, \
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{ "ieee-compare", MASK_IEEE_COMPARE, N_("Use IEEE math for fp comparisons")}, \
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{ "noieee-compare", -MASK_IEEE_COMPARE, \
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N_("Do not use IEEE math for fp comparisons")}, \
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{ "", TARGET_DEFAULT, 0}}
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/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */
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@ -166,14 +174,18 @@ extern int target_flags;
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/* When we are generating PIC, the sb is used as a pointer
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to the GOT. 32381 is a superset of 32081 */
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#define OVERRIDE_OPTIONS \
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{ \
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if (flag_pic || TARGET_HIMEM) \
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target_flags |= MASK_NO_SB; \
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if (TARGET_32381) \
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target_flags |= MASK_32081; \
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else \
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target_flags &= ~MASK_MULT_ADD; \
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#define OVERRIDE_OPTIONS \
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{ \
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if (target_flags & MASK_32532) \
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target_flags |= MASK_32332; \
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if (flag_pic || TARGET_HIMEM) \
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target_flags |= MASK_NO_SB; \
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if (TARGET_32381) \
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target_flags |= MASK_32081; \
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else \
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target_flags &= ~MASK_MULT_ADD; \
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if (flag_unsafe_math_optimizations) \
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target_flags &= ~MASK_IEEE_COMPARE; \
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}
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/* Zero or more C statements that may conditionally modify two
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@ -1180,6 +1192,10 @@ __transfer_from_trampoline () \
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is complemented in the F bit. */
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#define CC_Z_IN_NOT_F 010000
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/* This bit means that the L bit indicates unordered (IEEE) comparison.
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*/
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#define CC_UNORD 020000
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/* Store in cc_status the expressions
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that the condition codes will describe
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after execution of an instruction whose pattern is EXP.
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@ -94,6 +94,8 @@
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"TARGET_32081"
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"*
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{ cc_status.flags |= CC_REVERSED;
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if (TARGET_IEEE_COMPARE)
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cc_status.flags |= CC_UNORD;
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operands[1] = CONST0_RTX (DFmode);
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return \"cmpl %1,%0\"; }")
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@ -103,6 +105,8 @@
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"TARGET_32081"
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"*
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{ cc_status.flags |= CC_REVERSED;
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if (TARGET_IEEE_COMPARE)
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cc_status.flags |= CC_UNORD;
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operands[1] = CONST0_RTX (SFmode);
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return \"cmpf %1,%0\"; }")
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@ -202,14 +206,22 @@
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(compare (match_operand:DF 0 "general_operand" "lmF")
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(match_operand:DF 1 "general_operand" "lmF")))]
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"TARGET_32081"
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"cmpl %0,%1")
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"*
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{
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if (TARGET_IEEE_COMPARE)
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cc_status.flags |= CC_UNORD;
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return \"cmpl %0,%1\";}")
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(define_insn "cmpsf"
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[(set (cc0)
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(compare (match_operand:SF 0 "general_operand" "fmF")
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(match_operand:SF 1 "general_operand" "fmF")))]
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"TARGET_32081"
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"cmpf %0,%1")
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"*
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{
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if (TARGET_IEEE_COMPARE)
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cc_status.flags |= CC_UNORD;
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return \"cmpf %0,%1\";}")
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;; movdf and movsf copy between general and floating registers using
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;; the stack. In principle, we could get better code not allowing
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@ -798,7 +810,7 @@
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;; Multiply-add instructions
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(define_insn "*madddf"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,lm")
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[(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,&lm")
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(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
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(match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
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(match_operand:DF 3 "general_operand" "0,lmF,lmF")))]
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@ -809,7 +821,7 @@
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mull %2,%0\;addl %3,%0")
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(define_insn "*maddsf"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,fm")
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[(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,&fm")
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(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
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(match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
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(match_operand:SF 3 "general_operand" "0,fmF,fmF")))]
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@ -822,7 +834,7 @@
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;; Multiply-sub instructions
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(define_insn "*msubdf"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=v,lm")
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[(set (match_operand:DF 0 "nonimmediate_operand" "=&v,&lm")
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(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
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(match_operand:DF 2 "general_operand" "lmF,lmF"))
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(match_operand:DF 3 "general_operand" "lmF,lmF")))]
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@ -832,7 +844,7 @@
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mull %2,%0\;subl %3,%0")
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(define_insn "*msubsf"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=u,fm")
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[(set (match_operand:SF 0 "nonimmediate_operand" "=&u,&fm")
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(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
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(match_operand:SF 2 "general_operand" "fmF,fmF"))
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(match_operand:SF 3 "general_operand" "fmF,fmF")))]
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@ -883,20 +895,6 @@
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return \"adjspd %n0\";
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}")
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(define_insn "*frame_addr"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
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(plus:SI (reg:SI 24)
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(match_operand:SI 1 "immediate_operand" "i")))]
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"GET_CODE (operands[1]) == CONST_INT"
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"addr %c1(fp),%0")
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(define_insn "*stack_addr"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
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(plus:SI (reg:SI 25)
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(match_operand:SI 1 "immediate_operand" "i")))]
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"GET_CODE (operands[1]) == CONST_INT"
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"addr %c1(sp),%0")
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(define_insn "adddi3"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
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(plus:DI (match_operand:DI 1 "general_operand" "%0")
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@ -940,9 +938,9 @@
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;; See Note 1
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(define_insn "addsi3"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm&<")
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(plus:SI (match_operand:SI 1 "general_operand" "%0,r")
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(match_operand:SI 2 "general_operand" "g,i")))]
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[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm<,=rm<")
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(plus:SI (match_operand:SI 1 "general_operand" "%0,r,xy")
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(match_operand:SI 2 "general_operand" "g,i,i")))]
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""
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"*
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{
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@ -964,6 +962,14 @@
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return \"addr %c2(%1),%0\";
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}
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}
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else if (which_alternative == 2)
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{
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if (GET_CODE (operands[2]) == CONST_INT &&
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NS32K_DISPLACEMENT_P (INTVAL (operands[2])))
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return \"addr %c2(%1),%0\";
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else
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return \"sprd %1,%0\;addd %2,%0\";
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}
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else if (GET_CODE (operands[2]) == CONST_INT)
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{
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int i = INTVAL (operands[2]);
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@ -2313,7 +2319,13 @@
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(label_ref (match_operand 0 "" ""))
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(pc)))]
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""
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"blt %l0")
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"*
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{
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if (cc_prev_status.flags & CC_UNORD)
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return \"bhi 0f\;blt %l0\;0:\";
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else
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return \"blt %l0\";
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}")
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(define_insn "bltu"
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[(set (pc)
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@ -2349,7 +2361,13 @@
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(label_ref (match_operand 0 "" ""))
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(pc)))]
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""
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"ble %l0")
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"*
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{
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if (cc_prev_status.flags & CC_UNORD)
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return \"bhi 0f\;ble %l0\;0:\";
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else
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return \"ble %l0\";
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}")
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(define_insn "bleu"
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[(set (pc)
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@ -2399,7 +2417,13 @@
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(pc)
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(label_ref (match_operand 0 "" ""))))]
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""
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"ble %l0")
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"*
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{
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if (cc_prev_status.flags & CC_UNORD)
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return \"bhi 0f\;ble %l0\;0:\";
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else
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return \"ble %l0\";
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}")
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(define_insn "*bleu"
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[(set (pc)
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@ -2435,7 +2459,13 @@
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(pc)
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(label_ref (match_operand 0 "" ""))))]
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""
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"blt %l0")
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"*
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{
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if (cc_prev_status.flags & CC_UNORD)
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return \"bhi 0f\;blt %l0\;0:\";
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else
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return \"blt %l0\";
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}")
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(define_insn "*bltu"
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[(set (pc)
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@ -8698,6 +8698,15 @@ Do not try and generate multiply-add floating point instructions
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Generate output containing library calls for floating point.
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@strong{Warning:} the requisite libraries may not be available.
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@item -mieee-compare
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@itemx -mno-ieee-compare
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@opindex mieee-compare
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@opindex mno-ieee-compare
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Control whether or not the compiler uses IEEE floating point
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comparisons. These handle correctly the case where the result of a
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comparison is unordered.
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@strong{Warning:} the requisite kernel support may not be available.
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@item -mnobitfield
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@opindex mnobitfield
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Do not use the bit-field instructions. On some machines it is faster to
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