mirror of
git://gcc.gnu.org/git/gcc.git
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Use SImode instead of HImode if aligned.
From-SVN: r13479
This commit is contained in:
Stan Cox
parent
72acf258c6
commit
5bc7cd8eb8
@ -388,6 +388,85 @@ optimization_options (level)
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#endif
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}
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/* Sign-extend a 16-bit constant */
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struct rtx_def *
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i386_sext16_if_const (op)
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struct rtx_def *op;
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{
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if (GET_CODE (op) == CONST_INT)
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{
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HOST_WIDE_INT val = INTVAL (op);
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HOST_WIDE_INT sext_val;
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if (val & 0x8000)
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sext_val = val | ~0xffff;
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else
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sext_val = val & 0xffff;
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if (sext_val != val)
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op = GEN_INT (sext_val);
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}
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return op;
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}
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/* Return nonzero if the rtx is aligned */
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static int
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i386_aligned_reg_p (regno)
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int regno;
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{
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return (regno == STACK_POINTER_REGNUM
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|| (!flag_omit_frame_pointer
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&& regno == FRAME_POINTER_REGNUM));
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}
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int
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i386_aligned_p (op)
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rtx op;
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{
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/* registers and immediate operands are always "aligned" */
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if (GET_CODE (op) != MEM)
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return 1;
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/* Don't even try to do any aligned optimizations with volatiles */
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if (MEM_VOLATILE_P (op))
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return 0;
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/* Get address of memory operand */
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op = XEXP (op, 0);
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switch (GET_CODE (op))
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{
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case CONST_INT:
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if (INTVAL (op) & 3)
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break;
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return 1;
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/* match "reg + offset" */
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case PLUS:
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if (GET_CODE (XEXP (op, 1)) != CONST_INT)
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break;
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if (INTVAL (XEXP (op, 1)) & 3)
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break;
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op = XEXP (op, 0);
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if (GET_CODE (op) != REG)
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break;
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/* fall through */
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case REG:
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return i386_aligned_reg_p (REGNO (op));
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}
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return 0;
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}
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/* Return nonzero if INSN looks like it won't compute useful cc bits
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as a side effect. This information is only a hint. */
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int
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i386_cc_probably_useless_p (insn)
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rtx insn;
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{
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return !next_cc0_user (insn);
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}
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/* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
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attribute for DECL. The attributes in ATTRIBUTES have previously been
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assigned to DECL. */
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@ -854,7 +933,7 @@ asm_add (n, x)
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output_asm_insn (AS1 (dec%L0,%0), xops);
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else if (n == 1)
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output_asm_insn (AS1 (inc%L0,%0), xops);
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else if (n < 0)
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else if (n < 0 || n == 128)
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{
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xops[1] = GEN_INT (-n);
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output_asm_insn (AS2 (sub%L0,%1,%0), xops);
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@ -157,7 +157,8 @@ extern int target_flags;
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#define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
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#define TARGET_USE_LEAVE (ix86_cpu == PROCESSOR_I386)
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#define TARGET_PUSH_MEMORY (ix86_cpu == PROCESSOR_I386)
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#define TARGET_ZERO_EXTEND_WITH_AND (ix86_cpu != PROCESSOR_I386)
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#define TARGET_ZERO_EXTEND_WITH_AND (ix86_cpu != PROCESSOR_I386 \
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&& ix86_cpu != PROCESSOR_PENTIUMPRO)
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#define TARGET_DOUBLE_WITH_ADD (ix86_cpu != PROCESSOR_I386)
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#define TARGET_USE_BIT_TEST (ix86_cpu == PROCESSOR_I386)
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#define TARGET_UNROLL_STRLEN (ix86_cpu != PROCESSOR_I386)
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@ -2604,6 +2605,9 @@ do { \
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extern void override_options ();
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extern void order_regs_for_local_alloc ();
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extern char *output_strlen_unroll ();
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extern struct rtx_def *i386_sext16_if_const ();
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extern int i386_aligned_p ();
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extern int i386_cc_probably_useless_p ();
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extern int i386_valid_decl_attribute_p ();
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extern int i386_valid_type_attribute_p ();
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extern int i386_return_pops_args ();
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@ -770,6 +770,12 @@
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}
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}
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/* use 32-bit test instruction if there are no sign issues */
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if (GET_CODE (operands[1]) == CONST_INT
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&& !(INTVAL (operands[1]) & ~0x7fff)
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&& i386_aligned_p (operands[0]))
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return AS2 (test%L0,%1,%k0);
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if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
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return AS2 (test%W0,%1,%0);
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@ -931,10 +937,21 @@
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if (REG_P (operands[0]))
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{
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if (REG_P (operands[1]))
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return AS2 (mov%L0,%k1,%k0);
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else if (CONSTANT_P (operands[1]))
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return AS2 (mov%L0,%1,%k0);
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if (i386_aligned_p (operands[1]))
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{
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operands[1] = i386_sext16_if_const (operands[1]);
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return AS2 (mov%L0,%k1,%k0);
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}
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if (TARGET_PENTIUMPRO)
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{
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/* movzwl is faster than movw on the Pentium Pro,
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* although not as fast as an aligned movl. */
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#ifdef INTEL_SYNTAX
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return AS2 (movzx,%1,%k0);
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#else
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return AS2 (movz%W0%L0,%1,%k0);
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#endif
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}
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}
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return AS2 (mov%W0,%1,%0);
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@ -1040,7 +1057,7 @@
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{
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rtx link;
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if (operands[1] == const0_rtx && REG_P (operands[0]))
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return AS2 (xor%B0,%0,%0);
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return AS2 (xor%L0,%k0,%k0);
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if (operands[1] == const1_rtx
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&& (link = find_reg_note (insn, REG_WAS_0, 0))
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@ -1747,7 +1764,10 @@
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{
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xops[0] = operands[0];
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xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xffff);
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output_asm_insn (AS2 (mov%W0,%1,%w0),operands);
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if (i386_aligned_p (operands[1]))
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output_asm_insn (AS2 (mov%L0,%k1,%k0),operands);
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else
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output_asm_insn (AS2 (mov%W0,%1,%w0),operands);
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output_asm_insn (AS2 (and%L0,%1,%k0), xops);
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RET;
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}
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@ -2752,7 +2772,7 @@
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}")
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(define_insn "addsidi3_2"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,&r,!&r,r,o,o,!o")
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[(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,&r,!&r,&r,o,o,!o")
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(plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "o,ri,ri,o,o,ri,ri,i,r"))
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(match_operand:DI 1 "general_operand" "0,0,0,iF,ro,roiF,riF,o,o")))
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(clobber (match_scratch:SI 3 "=X,X,X,X,X,X,X,&r,&r"))]
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@ -2952,6 +2972,18 @@
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if (operands[2] == constm1_rtx)
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return AS1 (dec%L0,%0);
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/* subl $-128,%ebx is smaller than addl $128,%ebx. */
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if (GET_CODE (operands[2]) == CONST_INT
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&& INTVAL (operands[2]) == 128)
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{
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/* This doesn't compute the carry bit in the same way
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* as add%L0, but we use inc and dec above and they
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* don't set the carry bit at all. If inc/dec don't need
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* a CC_STATUS_INIT, this doesn't either... */
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operands[2] = GEN_INT (-128);
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return AS2 (sub%L0,%2,%0);
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}
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return AS2 (add%L0,%2,%0);
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}")
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@ -3003,9 +3035,11 @@
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"*
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{
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/* ??? what about offsettable memory references? */
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if (QI_REG_P (operands[0])
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if (!TARGET_PENTIUMPRO /* partial stalls are just too painful to risk. */
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&& QI_REG_P (operands[0])
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&& GET_CODE (operands[2]) == CONST_INT
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&& (INTVAL (operands[2]) & 0xff) == 0)
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&& (INTVAL (operands[2]) & 0xff) == 0
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&& i386_cc_probably_useless_p (insn))
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{
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int byteval = (INTVAL (operands[2]) >> 8) & 0xff;
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CC_STATUS_INIT;
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@ -3019,6 +3053,28 @@
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return AS2 (add%B0,%2,%h0);
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}
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/* Use a 32-bit operation when possible, to avoid the prefix penalty. */
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if (REG_P (operands[0])
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&& i386_aligned_p (operands[2])
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&& i386_cc_probably_useless_p (insn))
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{
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CC_STATUS_INIT;
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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HOST_WIDE_INT intval = 0xffff & INTVAL (operands[2]);
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if (intval == 1)
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return AS1 (inc%L0,%k0);
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if (intval == 0xffff)
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return AS1 (dec%L0,%k0);
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operands[2] = i386_sext16_if_const (operands[2]);
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}
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return AS2 (add%L0,%k2,%k0);
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}
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if (operands[2] == const1_rtx)
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return AS1 (inc%W0,%0);
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@ -3246,7 +3302,18 @@
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(minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
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(match_operand:HI 2 "general_operand" "ri,rm")))]
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"ix86_binary_operator_ok (MINUS, HImode, operands)"
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"* return AS2 (sub%W0,%2,%0);")
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"*
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{
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if (REG_P (operands[0])
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&& i386_aligned_p (operands[2])
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&& i386_cc_probably_useless_p (insn))
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{
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CC_STATUS_INIT;
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operands[2] = i386_sext16_if_const (operands[2]);
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return AS2 (sub%L0,%k2,%k0);
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}
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return AS2 (sub%W0,%2,%0);
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}")
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(define_expand "subqi3"
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[(set (match_operand:QI 0 "general_operand" "")
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@ -3518,7 +3585,6 @@
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;; The `r' in `rm' for operand 3 looks redundant, but it causes
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;; optional reloads to be generated if op 3 is a pseudo in a stack slot.
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;; ??? What if we only change one byte of an offsettable memory reference?
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(define_insn "andsi3"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
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(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
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@ -3526,6 +3592,7 @@
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""
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"*
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{
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HOST_WIDE_INT intval;
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if (!rtx_equal_p (operands[0], operands[1])
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&& rtx_equal_p (operands[0], operands[2]))
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{
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@ -3534,10 +3601,14 @@
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operands[1] = operands[2];
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operands[2] = tmp;
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}
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if (GET_CODE (operands[2]) == CONST_INT
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&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
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switch (GET_CODE (operands[2]))
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{
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if (INTVAL (operands[2]) == 0xffff && REG_P (operands[0])
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case CONST_INT:
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if (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
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break;
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intval = INTVAL (operands[2]);
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/* zero-extend 16->32? */
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if (intval == 0xffff && REG_P (operands[0])
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&& (! REG_P (operands[1])
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|| REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0)
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&& (!TARGET_ZERO_EXTEND_WITH_AND || ! rtx_equal_p (operands[0], operands[1])))
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@ -3552,7 +3623,8 @@
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#endif
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}
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if (INTVAL (operands[2]) == 0xff && REG_P (operands[0])
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/* zero extend 8->32? */
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if (intval == 0xff && REG_P (operands[0])
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&& !(REG_P (operands[1]) && NON_QI_REG_P (operands[1]))
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&& (! REG_P (operands[1])
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|| REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0)
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@ -3568,39 +3640,99 @@
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#endif
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}
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if (QI_REG_P (operands[0]) && ~(INTVAL (operands[2]) | 0xff) == 0)
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{
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CC_STATUS_INIT;
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/* Check partial bytes.. non-QI-regs are not available */
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if (REG_P (operands[0]) && ! QI_REG_P (operands[0]))
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break;
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if (INTVAL (operands[2]) == 0xffffff00)
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/* only low byte has zero bits? */
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if (~(intval | 0xff) == 0)
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{
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intval &= 0xff;
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if (REG_P (operands[0]))
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{
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operands[2] = const0_rtx;
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return AS2 (mov%B0,%2,%b0);
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if (intval == 0)
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{
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CC_STATUS_INIT;
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return AS2 (xor%B0,%b0,%b0);
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}
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/* we're better off with the 32-bit version if reg != EAX */
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/* the value is sign-extended in 8 bits */
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if (REGNO (operands[0]) != 0 && (intval & 0x80))
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break;
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}
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operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
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CC_STATUS_INIT;
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operands[2] = GEN_INT (intval);
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if (intval == 0)
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return AS2 (mov%B0,%2,%b0);
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return AS2 (and%B0,%2,%b0);
|
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}
|
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|
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if (QI_REG_P (operands[0]) && ~(INTVAL (operands[2]) | 0xff00) == 0)
|
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/* only second byte has zero? */
|
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if (~(intval | 0xff00) == 0)
|
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{
|
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CC_STATUS_INIT;
|
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|
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if (INTVAL (operands[2]) == 0xffff00ff)
|
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intval = (intval >> 8) & 0xff;
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operands[2] = GEN_INT (intval);
|
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if (intval == 0)
|
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{
|
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operands[2] = const0_rtx;
|
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return AS2 (mov%B0,%2,%h0);
|
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if (REG_P (operands[0]))
|
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return AS2 (xor%B0,%h0,%h0);
|
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operands[0] = adj_offsettable_operand (operands[0], 1);
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return AS2 (mov%B0,%2,%b0);
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}
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operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
|
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return AS2 (and%B0,%2,%h0);
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if (REG_P (operands[0]))
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return AS2 (and%B0,%2,%h0);
|
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|
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operands[0] = adj_offsettable_operand (operands[0], 1);
|
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return AS2 (and%B0,%2,%b0);
|
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}
|
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|
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if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) == 0xffff0000)
|
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if (REG_P (operands[0]))
|
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break;
|
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|
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/* third byte has zero bits? */
|
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if (~(intval | 0xff0000) == 0)
|
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{
|
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intval = (intval >> 16) & 0xff;
|
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operands[0] = adj_offsettable_operand (operands[0], 2);
|
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byte_and_operation:
|
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CC_STATUS_INIT;
|
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operands[2] = GEN_INT (intval);
|
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if (intval == 0)
|
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return AS2 (mov%B0,%2,%b0);
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return AS2 (and%B0,%2,%b0);
|
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}
|
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|
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/* fourth byte has zero bits? */
|
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if (~(intval | 0xff000000) == 0)
|
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{
|
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intval = (intval >> 24) & 0xff;
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operands[0] = adj_offsettable_operand (operands[0], 3);
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goto byte_and_operation;
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}
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/* Low word is zero? */
|
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if (intval == 0xffff0000)
|
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{
|
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word_zero_and_operation:
|
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CC_STATUS_INIT;
|
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operands[2] = const0_rtx;
|
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return AS2 (mov%W0,%2,%w0);
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}
|
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|
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/* High word is zero? */
|
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if (intval == 0x0000ffff)
|
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{
|
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operands[0] = adj_offsettable_operand (operands[0], 2);
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goto word_zero_and_operation;
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}
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}
|
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|
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return AS2 (and%L0,%2,%0);
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@ -3647,6 +3779,38 @@
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operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
|
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return AS2 (and%B0,%2,%h0);
|
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}
|
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|
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/* use 32-bit ops on registers when there are no sign issues.. */
|
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if (REG_P (operands[0]))
|
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{
|
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if (!(INTVAL (operands[2]) & ~0x7fff))
|
||||
return AS2 (and%L0,%2,%k0);
|
||||
}
|
||||
}
|
||||
|
||||
if (REG_P (operands[0])
|
||||
&& i386_aligned_p (operands[2]))
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
/* If op[2] is constant, we should zero-extend it and */
|
||||
/* make a note that op[0] has been zero-extended, so */
|
||||
/* that we could use 32-bit ops on it forthwith, but */
|
||||
/* there is no such reg-note available. Instead we do */
|
||||
/* a sign extension as that can result in shorter asm */
|
||||
operands[2] = i386_sext16_if_const (operands[2]);
|
||||
return AS2 (and%L0,%k2,%k0);
|
||||
}
|
||||
|
||||
/* Use a 32-bit word with the upper bits set, invalidate CC */
|
||||
if (GET_CODE (operands[2]) == CONST_INT
|
||||
&& i386_aligned_p (operands[0]))
|
||||
{
|
||||
HOST_WIDE_INT val = INTVAL (operands[2]);
|
||||
CC_STATUS_INIT;
|
||||
val |= ~0xffff;
|
||||
if (val != INTVAL (operands[2]))
|
||||
operands[2] = GEN_INT (val);
|
||||
return AS2 (and%L0,%k2,%k0);
|
||||
}
|
||||
|
||||
return AS2 (and%W0,%2,%0);
|
||||
@ -3685,7 +3849,10 @@
|
||||
|
||||
;;- Bit set (inclusive or) instructions
|
||||
|
||||
;; ??? What if we only change one byte of an offsettable memory reference?
|
||||
;; This optimizes known byte-wide operations to memory, and in some cases
|
||||
;; to QI registers.. Note that we don't want to use the QI registers too
|
||||
;; aggressively, because often the 32-bit register instruction is the same
|
||||
;; size, and likely to be faster on PentiumPro.
|
||||
(define_insn "iorsi3"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
|
||||
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
|
||||
@ -3693,29 +3860,76 @@
|
||||
""
|
||||
"*
|
||||
{
|
||||
if (GET_CODE (operands[2]) == CONST_INT
|
||||
&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
|
||||
HOST_WIDE_INT intval;
|
||||
switch (GET_CODE (operands[2]))
|
||||
{
|
||||
if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
|
||||
&& (INTVAL (operands[2]) & ~0xff) == 0)
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
case CONST_INT:
|
||||
|
||||
if (INTVAL (operands[2]) == 0xff)
|
||||
return AS2 (mov%B0,%2,%b0);
|
||||
if (REG_P (operands[0]) && ! QI_REG_P (operands[0]))
|
||||
break;
|
||||
|
||||
return AS2 (or%B0,%2,%b0);
|
||||
/* don't try to optimize volatile accesses */
|
||||
if (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
|
||||
break;
|
||||
|
||||
intval = INTVAL (operands[2]);
|
||||
if ((intval & ~0xff) == 0)
|
||||
{
|
||||
if (REG_P (operands[0]))
|
||||
{
|
||||
/* Do low byte access only for %eax or when high bit is set */
|
||||
if (REGNO (operands[0]) != 0 && !(intval & 0x80))
|
||||
break;
|
||||
}
|
||||
|
||||
byte_or_operation:
|
||||
CC_STATUS_INIT;
|
||||
|
||||
if (intval != INTVAL (operands[2]))
|
||||
operands[2] = GEN_INT (intval);
|
||||
|
||||
if (intval == 0xff)
|
||||
return AS2 (mov%B0,%2,%b0);
|
||||
|
||||
return AS2 (or%B0,%2,%b0);
|
||||
}
|
||||
|
||||
if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0)
|
||||
/* second byte? */
|
||||
if ((intval & ~0xff00) == 0)
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
operands[2] = GEN_INT (INTVAL (operands[2]) >> 8);
|
||||
intval >>= 8;
|
||||
|
||||
if (INTVAL (operands[2]) == 0xff)
|
||||
return AS2 (mov%B0,%2,%h0);
|
||||
if (REG_P (operands[0]))
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
operands[2] = GEN_INT (intval);
|
||||
if (intval == 0xff)
|
||||
return AS2 (mov%B0,%2,%h0);
|
||||
|
||||
return AS2 (or%B0,%2,%h0);
|
||||
return AS2 (or%B0,%2,%h0);
|
||||
}
|
||||
|
||||
operands[0] = adj_offsettable_operand (operands[0], 1);
|
||||
goto byte_or_operation;
|
||||
}
|
||||
|
||||
if (REG_P (operands[0]))
|
||||
break;
|
||||
|
||||
/* third byte? */
|
||||
if ((intval & ~0xff0000) == 0)
|
||||
{
|
||||
intval >>= 16;
|
||||
operands[0] = adj_offsettable_operand (operands[0], 2);
|
||||
goto byte_or_operation;
|
||||
}
|
||||
|
||||
/* fourth byte? */
|
||||
if ((intval & ~0xff000000) == 0)
|
||||
{
|
||||
intval = (intval >> 24) & 0xff;
|
||||
operands[0] = adj_offsettable_operand (operands[0], 3);
|
||||
goto byte_or_operation;
|
||||
}
|
||||
}
|
||||
|
||||
@ -3729,38 +3943,77 @@
|
||||
""
|
||||
"*
|
||||
{
|
||||
if (GET_CODE (operands[2]) == CONST_INT
|
||||
&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
|
||||
HOST_WIDE_INT intval;
|
||||
switch (GET_CODE (operands[2]))
|
||||
{
|
||||
/* Can we ignore the upper byte? */
|
||||
if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
|
||||
&& (INTVAL (operands[2]) & 0xff00) == 0)
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
if (INTVAL (operands[2]) & 0xffff0000)
|
||||
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
|
||||
case CONST_INT:
|
||||
|
||||
if (INTVAL (operands[2]) == 0xff)
|
||||
return AS2 (mov%B0,%2,%b0);
|
||||
if (REG_P (operands[0]) && ! QI_REG_P (operands[0]))
|
||||
break;
|
||||
|
||||
return AS2 (or%B0,%2,%b0);
|
||||
/* don't try to optimize volatile accesses */
|
||||
if (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
|
||||
break;
|
||||
|
||||
intval = 0xffff & INTVAL (operands[2]);
|
||||
|
||||
if ((intval & 0xff00) == 0)
|
||||
{
|
||||
if (REG_P (operands[0]))
|
||||
{
|
||||
/* Do low byte access only for %eax or when high bit is set */
|
||||
if (REGNO (operands[0]) != 0 && !(intval & 0x80))
|
||||
break;
|
||||
}
|
||||
|
||||
byte_or_operation:
|
||||
CC_STATUS_INIT;
|
||||
|
||||
if (intval == 0xff)
|
||||
return AS2 (mov%B0,%2,%b0);
|
||||
|
||||
return AS2 (or%B0,%2,%b0);
|
||||
}
|
||||
|
||||
/* Can we ignore the lower byte? */
|
||||
/* ??? what about offsettable memory references? */
|
||||
if (QI_REG_P (operands[0])
|
||||
&& (INTVAL (operands[2]) & 0xff) == 0)
|
||||
/* high byte? */
|
||||
if ((intval & 0xff) == 0)
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
|
||||
intval >>= 8;
|
||||
operands[2] = GEN_INT (intval);
|
||||
|
||||
if (INTVAL (operands[2]) == 0xff)
|
||||
return AS2 (mov%B0,%2,%h0);
|
||||
if (REG_P (operands[0]))
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
if (intval == 0xff)
|
||||
return AS2 (mov%B0,%2,%h0);
|
||||
|
||||
return AS2 (or%B0,%2,%h0);
|
||||
return AS2 (or%B0,%2,%h0);
|
||||
}
|
||||
|
||||
operands[0] = adj_offsettable_operand (operands[0], 1);
|
||||
|
||||
goto byte_or_operation;
|
||||
}
|
||||
}
|
||||
|
||||
if (REG_P (operands[0])
|
||||
&& i386_aligned_p (operands[2]))
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
operands[2] = i386_sext16_if_const (operands[2]);
|
||||
return AS2 (or%L0,%k2,%k0);
|
||||
}
|
||||
|
||||
if (GET_CODE (operands[2]) == CONST_INT
|
||||
&& i386_aligned_p (operands[0]))
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
intval = 0xffff & INTVAL (operands[2]);
|
||||
if (intval != INTVAL (operands[2]))
|
||||
operands[2] = GEN_INT (intval);
|
||||
return AS2 (or%L0,%2,%k0);
|
||||
}
|
||||
|
||||
return AS2 (or%W0,%2,%0);
|
||||
}")
|
||||
|
||||
@ -3773,7 +4026,6 @@
|
||||
|
||||
;;- xor instructions
|
||||
|
||||
;; ??? What if we only change one byte of an offsettable memory reference?
|
||||
(define_insn "xorsi3"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
|
||||
(xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
|
||||
@ -3781,29 +4033,76 @@
|
||||
""
|
||||
"*
|
||||
{
|
||||
if (GET_CODE (operands[2]) == CONST_INT
|
||||
&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
|
||||
HOST_WIDE_INT intval;
|
||||
switch (GET_CODE (operands[2]))
|
||||
{
|
||||
if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
|
||||
&& (INTVAL (operands[2]) & ~0xff) == 0)
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
case CONST_INT:
|
||||
|
||||
if (INTVAL (operands[2]) == 0xff)
|
||||
return AS1 (not%B0,%b0);
|
||||
if (REG_P (operands[0]) && ! QI_REG_P (operands[0]))
|
||||
break;
|
||||
|
||||
return AS2 (xor%B0,%2,%b0);
|
||||
/* don't try to optimize volatile accesses */
|
||||
if (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
|
||||
break;
|
||||
|
||||
intval = INTVAL (operands[2]);
|
||||
if ((intval & ~0xff) == 0)
|
||||
{
|
||||
if (REG_P (operands[0]))
|
||||
{
|
||||
/* Do low byte access only for %eax or when high bit is set */
|
||||
if (REGNO (operands[0]) != 0 && !(intval & 0x80))
|
||||
break;
|
||||
}
|
||||
|
||||
byte_xor_operation:
|
||||
CC_STATUS_INIT;
|
||||
|
||||
if (intval == 0xff)
|
||||
return AS1 (not%B0,%b0);
|
||||
|
||||
if (intval != INTVAL (operands[2]))
|
||||
operands[2] = GEN_INT (intval);
|
||||
return AS2 (xor%B0,%2,%b0);
|
||||
}
|
||||
|
||||
if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0)
|
||||
/* second byte? */
|
||||
if ((intval & ~0xff00) == 0)
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
operands[2] = GEN_INT (INTVAL (operands[2]) >> 8);
|
||||
intval >>= 8;
|
||||
|
||||
if (INTVAL (operands[2]) == 0xff)
|
||||
return AS1 (not%B0,%h0);
|
||||
if (REG_P (operands[0]))
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
if (intval == 0xff)
|
||||
return AS1 (not%B0,%h0);
|
||||
|
||||
return AS2 (xor%B0,%2,%h0);
|
||||
operands[2] = GEN_INT (intval);
|
||||
return AS2 (xor%B0,%2,%h0);
|
||||
}
|
||||
|
||||
operands[0] = adj_offsettable_operand (operands[0], 1);
|
||||
|
||||
goto byte_xor_operation;
|
||||
}
|
||||
|
||||
if (REG_P (operands[0]))
|
||||
break;
|
||||
|
||||
/* third byte? */
|
||||
if ((intval & ~0xff0000) == 0)
|
||||
{
|
||||
intval >>= 16;
|
||||
operands[0] = adj_offsettable_operand (operands[0], 2);
|
||||
goto byte_xor_operation;
|
||||
}
|
||||
|
||||
/* fourth byte? */
|
||||
if ((intval & ~0xff000000) == 0)
|
||||
{
|
||||
intval = (intval >> 24) & 0xff;
|
||||
operands[0] = adj_offsettable_operand (operands[0], 3);
|
||||
goto byte_xor_operation;
|
||||
}
|
||||
}
|
||||
|
||||
@ -3849,6 +4148,25 @@
|
||||
}
|
||||
}
|
||||
|
||||
if (REG_P (operands[0])
|
||||
&& i386_aligned_p (operands[2]))
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
operands[2] = i386_sext16_if_const (operands[2]);
|
||||
return AS2 (xor%L0,%k2,%k0);
|
||||
}
|
||||
|
||||
if (GET_CODE (operands[2]) == CONST_INT
|
||||
&& i386_aligned_p (operands[0]))
|
||||
{
|
||||
HOST_WIDE_INT intval;
|
||||
CC_STATUS_INIT;
|
||||
intval = 0xffff & INTVAL (operands[2]);
|
||||
if (intval != INTVAL (operands[2]))
|
||||
operands[2] = GEN_INT (intval);
|
||||
return AS2 (xor%L0,%2,%k0);
|
||||
}
|
||||
|
||||
return AS2 (xor%W0,%2,%0);
|
||||
}")
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user