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mips.c (mips_output_32bit_xfer): New function.
gcc/ * config/mips/mips.c (mips_output_32bit_xfer): New function. (mips_output_64bit_xfer): Likewise. (mips16_fp_args): Rename to... (mips_output_args_xfer): ...this and replace the FROM_FP_P argument with a DIRECTION argument. Use mips_output_32bit_xfer and mips_output_64bit_xfer. (build_mips16_function_stub): Update accordingly. (mips16_fpret_double): Delete. (build_mips16_call_stub): Update after above changes. Use mips_output_32bit_xfer. Use mips_output_64bit_xfer instead of mips16_fpret_double. Use GP_REG_RETURN. From-SVN: r129475
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
23fdf75ca5
commit
5b372d3337
@ -1,3 +1,17 @@
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2007-10-19 Richard Sandiford <rsandifo@nildram.co.uk>
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* config/mips/mips.c (mips_output_32bit_xfer): New function.
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(mips_output_64bit_xfer): Likewise.
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(mips16_fp_args): Rename to...
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(mips_output_args_xfer): ...this and replace the FROM_FP_P argument
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with a DIRECTION argument. Use mips_output_32bit_xfer and
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mips_output_64bit_xfer.
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(build_mips16_function_stub): Update accordingly.
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(mips16_fpret_double): Delete.
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(build_mips16_call_stub): Update after above changes.
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Use mips_output_32bit_xfer. Use mips_output_64bit_xfer instead
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of mips16_fpret_double. Use GP_REG_RETURN.
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2007-10-19 Richard Sandiford <rsandifo@nildram.co.uk>
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* config/mips/mips.c (mips16_fp_args): Remove the FILE argument and
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@ -5067,28 +5067,57 @@ mips16_call_stub_mode_suffix (enum machine_mode mode)
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gcc_unreachable ();
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}
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/* Write out code to move floating point arguments in or out of
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general registers. FP_CODE is the code describing which arguments
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are present (see the comment at the definition of CUMULATIVE_ARGS in
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mips.h). FROM_FP_P is nonzero if we are copying from the floating
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point registers. */
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/* Write instructions to move a 32-bit value between general register
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GPREG and floating-point register FPREG. DIRECTION is 't' to move
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from GPREG to FPREG and 'f' to move in the opposite direction. */
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static void
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mips16_fp_args (int fp_code, int from_fp_p)
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mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
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{
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const char *s;
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int gparg, fparg;
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unsigned int f;
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fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
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reg_names[gpreg], reg_names[fpreg]);
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}
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/* Likewise for 64-bit values. */
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static void
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mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
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{
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if (TARGET_64BIT)
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fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
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reg_names[gpreg], reg_names[fpreg]);
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else if (TARGET_FLOAT64)
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{
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fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
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reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
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fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
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reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
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}
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else
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{
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/* Move the least-significant word. */
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fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
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reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
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/* ...then the most significant word. */
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fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
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reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
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}
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}
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/* Write out code to move floating-point arguments into or out of
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general registers. FP_CODE is the code describing which arguments
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are present (see the comment above the definition of CUMULATIVE_ARGS
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in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
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static void
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mips_output_args_xfer (int fp_code, char direction)
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{
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unsigned int gparg, fparg, f;
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CUMULATIVE_ARGS cum;
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/* This code only works for the original 32-bit ABI and the O64 ABI. */
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gcc_assert (TARGET_OLDABI);
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if (from_fp_p)
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s = "mfc1";
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else
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s = "mtc1";
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init_cumulative_args (&cum, NULL, NULL);
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for (f = (unsigned int) fp_code; f != 0; f >>= 2)
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@ -5108,28 +5137,9 @@ mips16_fp_args (int fp_code, int from_fp_p)
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fparg = mips_arg_regno (&info, true);
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if (mode == SFmode)
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fprintf (asm_out_file, "\t%s\t%s,%s\n", s,
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reg_names[gparg], reg_names[fparg]);
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else if (TARGET_64BIT)
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fprintf (asm_out_file, "\td%s\t%s,%s\n", s,
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reg_names[gparg], reg_names[fparg]);
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else if (ISA_HAS_MXHC1)
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/* -mips32r2 -mfp64 */
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fprintf (asm_out_file, "\t%s\t%s,%s\n\t%s\t%s,%s\n",
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s,
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reg_names[gparg + (WORDS_BIG_ENDIAN ? 1 : 0)],
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reg_names[fparg],
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from_fp_p ? "mfhc1" : "mthc1",
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reg_names[gparg + (WORDS_BIG_ENDIAN ? 0 : 1)],
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reg_names[fparg]);
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else if (TARGET_BIG_ENDIAN)
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fprintf (asm_out_file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
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reg_names[gparg], reg_names[fparg + 1], s,
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reg_names[gparg + 1], reg_names[fparg]);
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mips_output_32bit_xfer (direction, gparg, fparg);
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else
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fprintf (asm_out_file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
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reg_names[gparg], reg_names[fparg], s,
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reg_names[gparg + 1], reg_names[fparg + 1]);
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mips_output_64bit_xfer (direction, gparg, fparg);
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function_arg_advance (&cum, mode, NULL, true);
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}
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@ -5193,7 +5203,7 @@ build_mips16_function_stub (void)
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/* We don't want the assembler to insert any nops here. */
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fprintf (asm_out_file, "\t.set\tnoreorder\n");
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mips16_fp_args (current_function_args_info.fp_code, 1);
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mips_output_args_xfer (current_function_args_info.fp_code, 'f');
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fprintf (asm_out_file, "\t.set\tnoat\n");
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fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
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@ -5221,47 +5231,6 @@ build_mips16_function_stub (void)
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switch_to_section (function_section (current_function_decl));
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}
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/* Emit code to return a double value from a mips16 stub. GPREG is the
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first GP reg to use, FPREG is the first FP reg to use. */
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static void
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mips16_fpret_double (int gpreg, int fpreg)
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{
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if (TARGET_64BIT)
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fprintf (asm_out_file, "\tdmfc1\t%s,%s\n",
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reg_names[gpreg], reg_names[fpreg]);
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else if (TARGET_FLOAT64)
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{
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fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
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reg_names[gpreg + WORDS_BIG_ENDIAN],
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reg_names[fpreg]);
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fprintf (asm_out_file, "\tmfhc1\t%s,%s\n",
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reg_names[gpreg + !WORDS_BIG_ENDIAN],
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reg_names[fpreg]);
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}
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else
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{
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if (TARGET_BIG_ENDIAN)
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{
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fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
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reg_names[gpreg + 0],
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reg_names[fpreg + 1]);
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fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
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reg_names[gpreg + 1],
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reg_names[fpreg + 0]);
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}
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else
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{
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fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
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reg_names[gpreg + 0],
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reg_names[fpreg + 0]);
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fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
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reg_names[gpreg + 1],
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reg_names[fpreg + 1]);
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}
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}
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}
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/* Build a call stub for a mips16 call. A stub is needed if we are
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passing any floating point values which should go into the floating
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point registers. If we are, and the call turns out to be to a
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@ -5452,7 +5421,7 @@ build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
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/* We don't want the assembler to insert any nops here. */
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fprintf (asm_out_file, "\t.set\tnoreorder\n");
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mips16_fp_args (fp_code, 0);
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mips_output_args_xfer (fp_code, 't');
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if (! fpret)
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{
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@ -5478,36 +5447,33 @@ build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
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switch (GET_MODE (retval))
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{
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case SCmode:
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fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
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reg_names[GP_REG_FIRST + 3],
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reg_names[FP_REG_FIRST + MAX_FPRS_PER_FMT]);
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mips_output_32bit_xfer ('f', GP_RETURN + 1,
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FP_REG_FIRST + MAX_FPRS_PER_FMT);
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/* Fall though. */
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case SFmode:
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fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
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reg_names[GP_REG_FIRST + 2],
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reg_names[FP_REG_FIRST + 0]);
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mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
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if (GET_MODE (retval) == SCmode && TARGET_64BIT)
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{
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/* On 64-bit targets, complex floats are returned in
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a single GPR, such that "sd" on a suitably-aligned
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target would store the value correctly. */
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fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
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reg_names[GP_REG_FIRST + 2 + TARGET_LITTLE_ENDIAN],
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reg_names[GP_REG_FIRST + 2 + TARGET_LITTLE_ENDIAN]);
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reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
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reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
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fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
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reg_names[GP_REG_FIRST + 2],
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reg_names[GP_REG_FIRST + 2],
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reg_names[GP_REG_FIRST + 3]);
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reg_names[GP_RETURN],
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reg_names[GP_RETURN],
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reg_names[GP_RETURN + 1]);
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}
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break;
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case DCmode:
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mips16_fpret_double (GP_REG_FIRST + 2 + (8 / UNITS_PER_WORD),
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FP_REG_FIRST + MAX_FPRS_PER_FMT);
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mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
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FP_REG_FIRST + MAX_FPRS_PER_FMT);
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/* Fall though. */
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case DFmode:
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case V2SFmode:
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mips16_fpret_double (GP_REG_FIRST + 2, FP_REG_FIRST + 0);
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mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
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break;
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default:
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