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znver3 tuning part 1
2021-03-15 Jan Hubicka <hubicka@ucw.cz> * config/i386/i386-options.c (processor_cost_table): Add znver3_cost. * config/i386/x86-tune-costs.h (znver3_cost): New gobal variable; copy of znver2_cost.
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Jan Hubicka
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52654036a5
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5b32a1817d
@ -743,7 +743,7 @@ static const struct processor_costs *processor_cost_table[] =
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&btver2_cost,
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&znver1_cost,
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&znver2_cost,
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&znver2_cost
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&znver3_cost
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};
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/* Guarantee that the array is aligned with enum processor_type. */
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@ -1688,6 +1688,140 @@ struct processor_costs znver2_cost = {
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"16", /* Func alignment. */
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};
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struct processor_costs znver3_cost = {
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{
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/* Start of register allocator costs. integer->integer move cost is 2. */
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/* reg-reg moves are done by renaming and thus they are even cheaper than
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1 cycle. Because reg-reg move cost is 2 and following tables correspond
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to doubles of latencies, we do not model this correctly. It does not
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seem to make practical difference to bump prices up even more. */
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6, /* cost for loading QImode using
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movzbl. */
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{6, 6, 6}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{8, 8, 8}, /* cost of storing integer
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registers. */
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2, /* cost of reg,reg fld/fst. */
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{6, 6, 16}, /* cost of loading fp registers
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in SFmode, DFmode and XFmode. */
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{8, 8, 16}, /* cost of storing fp registers
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in SFmode, DFmode and XFmode. */
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2, /* cost of moving MMX register. */
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{6, 6}, /* cost of loading MMX registers
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in SImode and DImode. */
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{8, 8}, /* cost of storing MMX registers
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in SImode and DImode. */
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2, 2, 3, /* cost of moving XMM,YMM,ZMM
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register. */
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{6, 6, 6, 6, 12}, /* cost of loading SSE registers
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in 32,64,128,256 and 512-bit. */
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{8, 8, 8, 8, 16}, /* cost of storing SSE registers
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in 32,64,128,256 and 512-bit. */
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6, 6, /* SSE->integer and integer->SSE
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moves. */
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8, 8, /* mask->integer and integer->mask moves */
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{6, 6, 6}, /* cost of loading mask register
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in QImode, HImode, SImode. */
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{8, 8, 8}, /* cost if storing mask register
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in QImode, HImode, SImode. */
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2, /* cost of moving mask register. */
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/* End of register allocator costs. */
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},
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COSTS_N_INSNS (1), /* cost of an add instruction. */
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COSTS_N_INSNS (1), /* cost of a lea instruction. */
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COSTS_N_INSNS (1), /* variable shift costs. */
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COSTS_N_INSNS (1), /* constant shift costs. */
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{COSTS_N_INSNS (3), /* cost of starting multiply for QI. */
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COSTS_N_INSNS (3), /* HI. */
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COSTS_N_INSNS (3), /* SI. */
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COSTS_N_INSNS (3), /* DI. */
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COSTS_N_INSNS (3)}, /* other. */
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0, /* cost of multiply per each bit
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set. */
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/* Depending on parameters, idiv can get faster on ryzen. This is upper
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bound. */
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{COSTS_N_INSNS (16), /* cost of a divide/mod for QI. */
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COSTS_N_INSNS (22), /* HI. */
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COSTS_N_INSNS (30), /* SI. */
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COSTS_N_INSNS (45), /* DI. */
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COSTS_N_INSNS (45)}, /* other. */
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COSTS_N_INSNS (1), /* cost of movsx. */
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COSTS_N_INSNS (1), /* cost of movzx. */
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8, /* "large" insn. */
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9, /* MOVE_RATIO. */
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6, /* CLEAR_RATIO */
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{6, 6, 6}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{8, 8, 8}, /* cost of storing integer
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registers. */
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{6, 6, 6, 6, 12}, /* cost of loading SSE registers
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in 32bit, 64bit, 128bit, 256bit and 512bit */
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{8, 8, 8, 8, 16}, /* cost of storing SSE register
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in 32bit, 64bit, 128bit, 256bit and 512bit */
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{6, 6, 6, 6, 12}, /* cost of unaligned loads. */
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{8, 8, 8, 8, 16}, /* cost of unaligned stores. */
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2, 2, 3, /* cost of moving XMM,YMM,ZMM
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register. */
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6, /* cost of moving SSE register to integer. */
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/* VGATHERDPD is 23 uops and throughput is 9, VGATHERDPD is 35 uops,
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throughput 12. Approx 9 uops do not depend on vector size and every load
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is 7 uops. */
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18, 8, /* Gather load static, per_elt. */
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18, 10, /* Gather store static, per_elt. */
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32, /* size of l1 cache. */
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512, /* size of l2 cache. */
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64, /* size of prefetch block. */
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/* New AMD processors never drop prefetches; if they cannot be performed
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immediately, they are queued. We set number of simultaneous prefetches
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to a large constant to reflect this (it probably is not a good idea not
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to limit number of prefetches at all, as their execution also takes some
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time). */
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100, /* number of parallel prefetches. */
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3, /* Branch cost. */
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COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
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COSTS_N_INSNS (5), /* cost of FMUL instruction. */
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/* Latency of fdiv is 8-15. */
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COSTS_N_INSNS (15), /* cost of FDIV instruction. */
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COSTS_N_INSNS (1), /* cost of FABS instruction. */
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COSTS_N_INSNS (1), /* cost of FCHS instruction. */
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/* Latency of fsqrt is 4-10. */
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COSTS_N_INSNS (10), /* cost of FSQRT instruction. */
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COSTS_N_INSNS (1), /* cost of cheap SSE instruction. */
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COSTS_N_INSNS (3), /* cost of ADDSS/SD SUBSS/SD insns. */
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COSTS_N_INSNS (3), /* cost of MULSS instruction. */
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COSTS_N_INSNS (3), /* cost of MULSD instruction. */
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COSTS_N_INSNS (5), /* cost of FMA SS instruction. */
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COSTS_N_INSNS (5), /* cost of FMA SD instruction. */
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COSTS_N_INSNS (10), /* cost of DIVSS instruction. */
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/* 9-13. */
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COSTS_N_INSNS (13), /* cost of DIVSD instruction. */
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COSTS_N_INSNS (10), /* cost of SQRTSS instruction. */
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COSTS_N_INSNS (15), /* cost of SQRTSD instruction. */
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/* Zen can execute 4 integer operations per cycle. FP operations
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take 3 cycles and it can execute 2 integer additions and 2
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multiplications thus reassociation may make sense up to with of 6.
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SPEC2k6 bencharks suggests
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that 4 works better than 6 probably due to register pressure.
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Integer vector operations are taken by FP unit and execute 3 vector
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plus/minus operations per cycle but only one multiply. This is adjusted
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in ix86_reassociation_width. */
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4, 4, 3, 6, /* reassoc int, fp, vec_int, vec_fp. */
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znver2_memcpy,
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znver2_memset,
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COSTS_N_INSNS (4), /* cond_taken_branch_cost. */
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COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */
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"16", /* Loop alignment. */
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"16", /* Jump alignment. */
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"0:0:8", /* Label alignment. */
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"16", /* Func alignment. */
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};
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/* skylake_cost should produce code tuned for Skylake familly of CPUs. */
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static stringop_algs skylake_memcpy[2] = {
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{libcall, {{1024, rep_prefix_4_byte, true}, {-1, libcall, false}}},
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