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pru: Add builtins for HALT and LMBD
Add builtins for HALT and LMBD, per Texas Instruments document SPRUHV7C. Use the new LMBD pattern to define an expand for clz. Binutils [1] and sim [2] support for LMBD instruction are merged now. [1] https://sourceware.org/pipermail/binutils/2020-October/113901.html [2] https://sourceware.org/pipermail/gdb-patches/2020-November/173141.html gcc/ChangeLog: * config/pru/alu-zext.md: Add lmbd patterns for zero_extend variants. * config/pru/pru.c (enum pru_builtin): Add HALT and LMBD. (pru_init_builtins): Ditto. (pru_builtin_decl): Ditto. (pru_expand_builtin): Ditto. * config/pru/pru.h (CLZ_DEFINED_VALUE_AT_ZERO): Define PRU value for CLZ with zero value parameter. * config/pru/pru.md: Add halt, lmbd and clz patterns. * doc/extend.texi: Document PRU builtins. gcc/testsuite/ChangeLog: * gcc.target/pru/halt.c: New test. * gcc.target/pru/lmbd.c: New test.
This commit is contained in:
Dimitar Dimitrov
parent
0b0061f4d8
commit
5ace1776b8
@ -37,6 +37,10 @@
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(define_subst_attr "alu3_zext_op2" "alu3_zext_op2_subst" "_z2" "_noz2")
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(define_subst_attr "alu3_zext" "alu3_zext_subst" "_z" "_noz")
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(define_subst_attr "lmbd_zext_op1" "lmbd_zext_op1_subst" "_z1" "_noz1")
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(define_subst_attr "lmbd_zext_op2" "lmbd_zext_op2_subst" "_z2" "_noz2")
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(define_subst_attr "lmbd_zext" "lmbd_zext_subst" "_z" "_noz")
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(define_subst_attr "bitalu_zext" "bitalu_zext_subst" "_z" "_noz")
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(define_code_iterator ALUOP3 [plus minus and ior xor umin umax ashift lshiftrt])
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@ -72,6 +76,19 @@
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[(set_attr "type" "alu")])
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;; Left Most Bit Detect instruction.
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(define_insn "pru_lmbd_impl<EQD:mode><EQS0:mode><EQS1:mode>_<lmbd_zext><lmbd_zext_op1><lmbd_zext_op2>"
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[(set (match_operand:EQD 0 "register_operand" "=r")
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(unspec:EQD
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[(zero_extend:EQD
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(match_operand:EQS0 1 "register_operand" "r"))
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(zero_extend:EQD
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(match_operand:EQS1 2 "reg_or_ubyte_operand" "r<EQS1:ubyte_constr>"))]
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UNSPEC_LMBD))]
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""
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"lmbd\t%0, %1, %2"
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[(set_attr "type" "alu")])
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(define_insn "neg_impl<EQD:mode><EQS0:mode>_<alu2_zext>"
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[(set (match_operand:EQD 0 "register_operand" "=r")
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(neg:EQD
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@ -179,3 +196,37 @@
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[(set (match_dup 0)
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(ALUOP3:EQD (zero_extend:EQD (match_dup 1))
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(match_dup 2)))])
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(define_subst "lmbd_zext_subst"
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[(set (match_operand:EQD 0)
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(unspec:EQD [(zero_extend:EQD (match_operand:EQD 1))
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(zero_extend:EQD (match_operand:EQD 2))]
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UNSPEC_LMBD))]
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""
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[(set (match_dup 0)
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(unspec:EQD [(match_dup 1)
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(match_dup 2)]
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UNSPEC_LMBD))])
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(define_subst "lmbd_zext_op1_subst"
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[(set (match_operand:EQD 0)
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(unspec:EQD [(zero_extend:EQD (match_operand:EQD 1))
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(zero_extend:EQD (match_operand:EQS1 2))]
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UNSPEC_LMBD))]
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""
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[(set (match_dup 0)
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(unspec:EQD [(match_dup 1)
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(zero_extend:EQD (match_dup 2))]
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UNSPEC_LMBD))])
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(define_subst "lmbd_zext_op2_subst"
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[(set (match_operand:EQD 0)
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(unspec:EQD [(zero_extend:EQD (match_operand:EQD 1))
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(zero_extend:EQD (match_operand:EQD 2))]
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UNSPEC_LMBD))]
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""
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[(set (match_dup 0)
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(unspec:EQD [(zero_extend:EQD (match_dup 1))
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(match_dup 2)]
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UNSPEC_LMBD))])
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@ -2705,6 +2705,8 @@ pru_reorg (void)
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enum pru_builtin
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{
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PRU_BUILTIN_DELAY_CYCLES,
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PRU_BUILTIN_HALT,
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PRU_BUILTIN_LMBD,
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PRU_BUILTIN_max
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};
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@ -2719,11 +2721,31 @@ pru_init_builtins (void)
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= build_function_type_list (void_type_node,
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long_long_integer_type_node,
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NULL);
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tree uint_ftype_uint_uint
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= build_function_type_list (unsigned_type_node,
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unsigned_type_node,
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unsigned_type_node,
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NULL);
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tree void_ftype_void
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= build_function_type_list (void_type_node,
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void_type_node,
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NULL);
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pru_builtins[PRU_BUILTIN_DELAY_CYCLES]
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= add_builtin_function ("__delay_cycles", void_ftype_longlong,
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PRU_BUILTIN_DELAY_CYCLES, BUILT_IN_MD, NULL,
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NULL_TREE);
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pru_builtins[PRU_BUILTIN_HALT]
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= add_builtin_function ("__halt", void_ftype_void,
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PRU_BUILTIN_HALT, BUILT_IN_MD, NULL,
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NULL_TREE);
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pru_builtins[PRU_BUILTIN_LMBD]
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= add_builtin_function ("__lmbd", uint_ftype_uint_uint,
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PRU_BUILTIN_LMBD, BUILT_IN_MD, NULL,
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NULL_TREE);
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}
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/* Implement TARGET_BUILTIN_DECL. */
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@ -2734,6 +2756,8 @@ pru_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
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switch (code)
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{
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case PRU_BUILTIN_DELAY_CYCLES:
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case PRU_BUILTIN_HALT:
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case PRU_BUILTIN_LMBD:
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return pru_builtins[code];
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default:
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return error_mark_node;
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@ -2806,19 +2830,45 @@ pru_expand_delay_cycles (rtx arg)
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IGNORE is nonzero if the value is to be ignored. */
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static rtx
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pru_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
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pru_expand_builtin (tree exp, rtx target,
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rtx subtarget ATTRIBUTE_UNUSED,
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machine_mode mode ATTRIBUTE_UNUSED,
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machine_mode mode,
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int ignore ATTRIBUTE_UNUSED)
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{
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tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
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unsigned int fcode = DECL_MD_FUNCTION_CODE (fndecl);
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rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
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if (fcode == PRU_BUILTIN_DELAY_CYCLES)
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return pru_expand_delay_cycles (arg1);
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switch (fcode)
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{
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case PRU_BUILTIN_DELAY_CYCLES:
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{
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rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
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return pru_expand_delay_cycles (arg1);
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}
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break;
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case PRU_BUILTIN_HALT:
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{
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emit_insn (gen_pru_halt ());
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return NULL_RTX;
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}
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break;
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case PRU_BUILTIN_LMBD:
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{
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rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
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rtx arg2 = expand_normal (CALL_EXPR_ARG (exp, 1));
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internal_error ("bad builtin code");
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if (target == NULL_RTX || GET_MODE (target) != mode)
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{
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target = gen_reg_rtx (mode);
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}
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emit_insn (gen_pru_lmbd (mode, target, arg1, arg2));
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return target;
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}
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break;
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default:
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internal_error ("bad builtin code");
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}
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return NULL_RTX;
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}
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@ -562,6 +562,9 @@ do { \
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#define CASE_VECTOR_MODE Pmode
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/* See definition of clz pattern for rationale of value -1. */
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#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2)
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/* Jumps are cheap on PRU. */
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#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
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@ -51,6 +51,10 @@
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;; Enumeration of UNSPECs.
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(define_c_enum "unspec" [
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UNSPEC_LMBD
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])
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(define_c_enum "unspecv" [
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UNSPECV_DELAY_CYCLES_START
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UNSPECV_DELAY_CYCLES_END
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@ -61,6 +65,8 @@
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UNSPECV_LOOP_BEGIN
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UNSPECV_LOOP_END
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UNSPECV_HALT
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UNSPECV_BLOCKAGE
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])
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@ -1020,3 +1026,37 @@
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""
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"nop\\t# Loop end guard"
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[(set_attr "type" "alu")])
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;; HALT instruction.
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(define_insn "pru_halt"
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[(unspec_volatile [(const_int 0)] UNSPECV_HALT)]
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""
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"halt"
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[(set_attr "type" "control")])
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;; Count Leading Zeros implemented using LMBD.
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;; LMBD returns 32 if bit value is not present, and we subtract 31 to get CLZ.
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;; Hence we get a defined value -1 for CLZ_DEFINED_VALUE_AT_ZERO.
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(define_expand "clz<mode>2"
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[(set (match_operand:QISI 0 "register_operand")
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(clz:QISI (match_operand:QISI 1 "register_operand")))]
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""
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{
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rtx dst = operands[0];
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rtx src = operands[1];
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rtx tmpval = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_pru_lmbd (<MODE>mode, tmpval, src, const1_rtx));
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emit_insn (gen_sub3_insn (dst, GEN_INT (31), tmpval));
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DONE;
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})
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;; Left Most Bit Detect operation, which maps to a single instruction.
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(define_expand "@pru_lmbd<mode>"
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[(set (match_operand:QISI 0 "register_operand")
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(unspec:QISI
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[(match_operand:QISI 1 "register_operand")
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(match_operand:QISI 2 "reg_or_ubyte_operand")]
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UNSPEC_LMBD))]
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""
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"")
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@ -14154,6 +14154,7 @@ instructions, but allow the compiler to schedule those calls.
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* PowerPC Hardware Transactional Memory Built-in Functions::
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* PowerPC Atomic Memory Operation Functions::
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* PowerPC Matrix-Multiply Assist Built-in Functions::
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* PRU Built-in Functions::
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* RISC-V Built-in Functions::
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* RX Built-in Functions::
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* S/390 System z Built-in Functions::
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@ -21934,6 +21935,33 @@ vec_t __builtin_vsx_xvcvspbf16 (vec_t);
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vec_t __builtin_vsx_xvcvbf16spn (vec_t);
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@end smallexample
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@node PRU Built-in Functions
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@subsection PRU Built-in Functions
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GCC provides a couple of special builtin functions to aid in utilizing
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special PRU instructions.
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The built-in functions supported are:
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@table @code
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@item __delay_cycles (long long @var{cycles})
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This inserts an instruction sequence that takes exactly @var{cycles}
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cycles (between 0 and 0xffffffff) to complete. The inserted sequence
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may use jumps, loops, or no-ops, and does not interfere with any other
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instructions. Note that @var{cycles} must be a compile-time constant
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integer - that is, you must pass a number, not a variable that may be
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optimized to a constant later. The number of cycles delayed by this
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builtin is exact.
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@item __halt (void)
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This inserts a HALT instruction to stop processor execution.
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@item unsigned int __lmbd (unsigned int @var{wordval}, unsigned int @var{bitval})
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This inserts LMBD instruction to calculate the left-most bit with value
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@var{bitval} in value @var{wordval}. Only the least significant bit
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of @var{bitval} is taken into account.
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@end table
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@node RISC-V Built-in Functions
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@subsection RISC-V Built-in Functions
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9
gcc/testsuite/gcc.target/pru/halt.c
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9
gcc/testsuite/gcc.target/pru/halt.c
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@ -0,0 +1,9 @@
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/* Test HALT builtin. */
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void
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test_halt (void)
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{
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/* { dg-final { scan-assembler "halt" } } */
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__halt();
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}
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14
gcc/testsuite/gcc.target/pru/lmbd.c
Normal file
14
gcc/testsuite/gcc.target/pru/lmbd.c
Normal file
@ -0,0 +1,14 @@
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/* Test LMBD builtin. */
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/* { dg-options "-O1" } */
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/* -O1 in the options is significant. Without it zero_extend
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operation may not be optimized. */
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unsigned int
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test_lmbd (unsigned char a, unsigned short b)
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{
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/* { dg-final { scan-assembler "lmbd\\tr14, r14.w1, r14.b0" } } */
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return __lmbd(b, a);
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}
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