mirror/gcc
2
0
Fork 0
mirror of git://gcc.gnu.org/git/gcc.git synced 2025-03-28 16:01:00 +08:00
Code Issues Packages Projects Releases Wiki Activity

rs6000: Make all insert instructions one type

Browse Source 
This uses the attribute "size" to specify the differences:

	insert_word  -> insert size=32
	insert_dword -> insert size=64

It could use "dot" as well, but the current code doesn't handle that.

From-SVN: r210868
This commit is contained in:
Segher Boessenkool 2014-05-23 18:37:55 +02:00 committed by Segher Boessenkool
parent e0528ed9e5
commit 58ee9e6635
26 changed files with 93 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
gcc/ChangeLog
View File

@ -1,3 +1,39 @@
2014-05-23 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (type): Delete "insert_word",
"insert_dword". Add "insert".
(size): Update comment.
* config/rs6000/rs6000.c (rs6000_adjust_cost, is_cracked_insn,
insn_must_be_first_in_group): Adjust.
(insvsi_internal, *insvsi_internal1, *insvsi_internal2,
*insvsi_internal3, *insvsi_internal4, *insvsi_internal5,
*insvsi_internal6, insvdi_internal): Adjust.
* config/rs6000/40x.md (ppc403-integer): Adjust.
* config/rs6000/440.md (ppc440-integer): Adjust.
* config/rs6000/476.md (ppc476-simple-integer): Adjust.
* config/rs6000/601.md (ppc601-integer): Adjust.
* config/rs6000/603.md (ppc603-integer): Adjust.
* config/rs6000/6xx.md (ppc604-integer): Adjust.
* config/rs6000/7450.md (ppc7450-integer): Adjust.
* config/rs6000/7xx.md (ppc750-integer): Adjust.
* config/rs6000/8540.md (ppc8540_su): Adjust.
* config/rs6000/cell.md (cell-integer, cell-insert): Adjust.
* config/rs6000/e300c2c3.md (ppce300c3_iu): Adjust.
* config/rs6000/e500mc.md (e500mc_su): Adjust.
* config/rs6000/e500mc64.md (e500mc64_su): Adjust.
* config/rs6000/e5500.md (e5500_sfx): Adjust.
* config/rs6000/e6500.md (e6500_sfx): Adjust.
* config/rs6000/mpc.md (mpccore-integer): Adjust.
* config/rs6000/power4.md (power4-integer, power4-insert): Adjust.
* config/rs6000/power5.md (power5-integer, power5-insert): Adjust.
* config/rs6000/power6.md (power6-insert, power6-insert-dword):
Adjust.
* config/rs6000/power7.md (power7-integer): Adjust.
* config/rs6000/power8.md (power8-1cyc): Adjust.
* config/rs6000/rs64.md (rs64a-integer): Adjust.
* config/rs6000/titan.md (titan_fxu_shift_and_rotate): Adjust.
2014-05-23 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (type): Add "mul". Delete "imul",

2
gcc/config/rs6000/40x.md
View File

@ -36,7 +36,7 @@
"iu_40x")
(define_insn_reservation "ppc403-integer" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
(and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")

2
gcc/config/rs6000/440.md
View File

@ -53,7 +53,7 @@
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
(and (eq_attr "type" "integer,insert,shift,\
trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")

2
gcc/config/rs6000/476.md
View File

@ -63,7 +63,7 @@
ppc476_lj_pipe")
(define_insn_reservation "ppc476-simple-integer" 1
(and (eq_attr "type" "integer,insert_word,var_shift_rotate,exts,shift")
(and (eq_attr "type" "integer,insert,var_shift_rotate,exts,shift")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe|ppc476_lj_pipe")

2
gcc/config/rs6000/601.md
View File

@ -45,7 +45,7 @@
"iu_ppc601+fpu_ppc601")
(define_insn_reservation "ppc601-integer" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
(and (eq_attr "type" "integer,insert,shift,\
trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc601"))
"iu_ppc601")

2
gcc/config/rs6000/603.md
View File

@ -58,7 +58,7 @@
"lsu_603")
(define_insn_reservation "ppc603-integer" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
(and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc603"))
"iu_603")

2
gcc/config/rs6000/6xx.md
View File

@ -73,7 +73,7 @@
"lsu_6xx")
(define_insn_reservation "ppc604-integer" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
(and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")

2
gcc/config/rs6000/7450.md
View File

@ -73,7 +73,7 @@
"ppc7450_du,lsu_7450")
(define_insn_reservation "ppc7450-integer" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
(and (eq_attr "type" "integer,insert,shift,\
trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")

2
gcc/config/rs6000/7xx.md
View File

@ -61,7 +61,7 @@
"ppc750_du,lsu_7xx")
(define_insn_reservation "ppc750-integer" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
(and (eq_attr "type" "integer,insert,shift,\
trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx")

2
gcc/config/rs6000/8540.md
View File

@ -84,7 +84,7 @@
;; Simple SU insns
(define_insn_reservation "ppc8540_su" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\
(and (eq_attr "type" "integer,insert,cmp,compare,\
delayed_compare,var_delayed_compare,fast_compare,\
shift,trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc8540,ppc8548"))

9
gcc/config/rs6000/cell.md
View File

@ -166,8 +166,10 @@
;; Integer latency is 2 cycles
(define_insn_reservation "cell-integer" 2
(and (eq_attr "type" "integer,insert_dword,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(and (ior (eq_attr "type" "integer,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
(eq_attr "cpu" "cell"))
"slot01,fxu_cell")
@ -185,7 +187,8 @@
;; rlwimi, alter cr0
(define_insn_reservation "cell-insert" 2
(and (eq_attr "type" "insert_word")
(and (eq_attr "type" "insert")
(eq_attr "size" "32")
(eq_attr "cpu" "cell"))
"slot01,fxu_cell")

2
gcc/config/rs6000/e300c2c3.md
View File

@ -90,7 +90,7 @@
;; Other one cycle IU insns
(define_insn_reservation "ppce300c3_iu" 1
(and (eq_attr "type" "integer,insert_word,isel")
(and (eq_attr "type" "integer,insert,isel")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")

2
gcc/config/rs6000/e500mc.md
View File

@ -70,7 +70,7 @@
;; Simple SU insns.
(define_insn_reservation "e500mc_su" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\
(and (eq_attr "type" "integer,insert,cmp,compare,\
delayed_compare,var_delayed_compare,fast_compare,\
shift,trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppce500mc"))

2
gcc/config/rs6000/e500mc64.md
View File

@ -69,7 +69,7 @@
;; Simple SU insns.
(define_insn_reservation "e500mc64_su" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
(and (eq_attr "type" "integer,insert,delayed_compare,\
shift,cntlz,exts")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")

2
gcc/config/rs6000/e5500.md
View File

@ -56,7 +56,7 @@
;; SFX.
(define_insn_reservation "e5500_sfx" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
(and (eq_attr "type" "integer,insert,delayed_compare,\
shift,cntlz,exts")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")

2
gcc/config/rs6000/e6500.md
View File

@ -59,7 +59,7 @@
;; SFX.
(define_insn_reservation "e6500_sfx" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
(and (eq_attr "type" "integer,insert,delayed_compare,\
shift,cntlz,exts")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")

2
gcc/config/rs6000/mpc.md
View File

@ -41,7 +41,7 @@
"lsu_mpc")
(define_insn_reservation "mpccore-integer" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
(and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "mpccore"))
"iu_mpc")

9
gcc/config/rs6000/power4.md
View File

@ -210,8 +210,10 @@
; Integer latency is 2 cycles
(define_insn_reservation "power4-integer" 2
(and (eq_attr "type" "integer,insert_dword,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(and (ior (eq_attr "type" "integer,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
(eq_attr "cpu" "power4"))
"iq_power4")
@ -238,7 +240,8 @@
|(iu1_power4,nothing,iu1_power4,nothing,iu2_power4))")
(define_insn_reservation "power4-insert" 4
(and (eq_attr "type" "insert_word")
(and (eq_attr "type" "insert")
(eq_attr "size" "32")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
((iu1_power4,nothing,iu2_power4)\

9
gcc/config/rs6000/power5.md
View File

@ -166,8 +166,10 @@
; Integer latency is 2 cycles
(define_insn_reservation "power5-integer" 2
(and (eq_attr "type" "integer,insert_dword,shift,trap,\
var_shift_rotate,cntlz,exts,isel,popcnt")
(and (ior (eq_attr "type" "integer,shift,trap,\
var_shift_rotate,cntlz,exts,isel,popcnt")
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
(eq_attr "cpu" "power5"))
"iq_power5")
@ -194,7 +196,8 @@
|(iu1_power5,nothing,iu2_power5,nothing,iu2_power5))")
(define_insn_reservation "power5-insert" 4
(and (eq_attr "type" "insert_word")
(and (eq_attr "type" "insert")
(eq_attr "size" "32")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")

6
gcc/config/rs6000/power6.md
View File

@ -247,12 +247,14 @@
"FXU_power6")
(define_insn_reservation "power6-insert" 1
(and (eq_attr "type" "insert_word")
(and (eq_attr "type" "insert")
(eq_attr "size" "32")
(eq_attr "cpu" "power6"))
"FX2_power6")
(define_insn_reservation "power6-insert-dword" 1
(and (eq_attr "type" "insert_dword")
(and (eq_attr "type" "insert")
(eq_attr "size" "64")
(eq_attr "cpu" "power6"))
"FX2_power6")

2
gcc/config/rs6000/power7.md
View File

@ -174,7 +174,7 @@
; FX Unit
(define_insn_reservation "power7-integer" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
(and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,exts,isel,popcnt")
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")

2
gcc/config/rs6000/power8.md
View File

@ -168,7 +168,7 @@
; FX Unit
(define_insn_reservation "power8-1cyc" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
(and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,exts,isel")
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")

12
gcc/config/rs6000/rs6000.c
View File

@ -26240,8 +26240,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
case TYPE_SHIFT:
case TYPE_INSERT_WORD:
case TYPE_INSERT_DWORD:
case TYPE_INSERT:
{
if (! store_data_bypass_p (dep_insn, insn))
return 3;
@ -26311,8 +26310,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
case TYPE_SHIFT:
case TYPE_INSERT_WORD:
case TYPE_INSERT_DWORD:
case TYPE_INSERT:
{
if (set_to_load_agen (dep_insn, insn))
return 3;
@ -26495,7 +26493,8 @@ is_cracked_insn (rtx insn)
|| (type == TYPE_MUL
&& get_attr_dot (insn) == DOT_YES)
|| type == TYPE_IDIV || type == TYPE_LDIV
|| type == TYPE_INSERT_WORD)
|| (type == TYPE_INSERT
&& get_attr_size (insn) == SIZE_32))
return true;
}
@ -27320,7 +27319,6 @@ insn_must_be_first_in_group (rtx insn)
switch (type)
{
case TYPE_INSERT_DWORD:
case TYPE_EXTS:
case TYPE_CNTLZ:
case TYPE_SHIFT:
@ -27328,7 +27326,7 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_TRAP:
case TYPE_MUL:
case TYPE_IDIV:
case TYPE_INSERT_WORD:
case TYPE_INSERT:
case TYPE_DELAYED_COMPARE:
case TYPE_FPCOMPARE:
case TYPE_MFCR:

21
gcc/config/rs6000/rs6000.md
View File

@ -159,7 +159,7 @@
;; computations.
(define_attr "type"
"integer,two,three,
shift,var_shift_rotate,insert_word,insert_dword,
shift,var_shift_rotate,insert,
mul,halfmul,idiv,ldiv,
exts,cntlz,popcnt,isel,
load,store,fpload,fpstore,vecload,vecstore,
@ -175,7 +175,7 @@
(const_string "integer"))
;; What data size does this instruction work on?
;; This is used for mul.
;; This is used for insert, mul.
(define_attr "size" "8,16,32,64" (const_string "32"))
;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
@ -3417,7 +3417,7 @@
operands[1] = GEN_INT (start + size - 1);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
[(set_attr "type" "insert")])
(define_insn "*insvsi_internal1"
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
@ -3436,7 +3436,7 @@
operands[1] = GEN_INT (start + size - 1);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
[(set_attr "type" "insert")])
(define_insn "*insvsi_internal2"
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
@ -3455,7 +3455,7 @@
operands[1] = GEN_INT (start + size - 1);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
[(set_attr "type" "insert")])
(define_insn "*insvsi_internal3"
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
@ -3474,7 +3474,7 @@
operands[1] = GEN_INT (start + size - 1);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
[(set_attr "type" "insert")])
(define_insn "*insvsi_internal4"
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
@ -3496,7 +3496,7 @@
operands[1] = GEN_INT (insert_start + insert_size - 1);
return \"rlwimi %0,%3,%h5,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
[(set_attr "type" "insert")])
;; combine patterns for rlwimi
(define_insn "*insvsi_internal5"
@ -3516,7 +3516,7 @@
operands[1] = GEN_INT(me);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
[(set_attr "type" "insert")])
(define_insn "*insvsi_internal6"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@ -3535,7 +3535,7 @@
operands[1] = GEN_INT(me);
return \"rlwimi %0,%3,%h4,%h2,%h1\";
}"
[(set_attr "type" "insert_word")])
[(set_attr "type" "insert")])
(define_insn "insvdi_internal"
[(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
@ -3551,7 +3551,8 @@
operands[1] = GEN_INT (64 - start - size);
return \"rldimi %0,%3,%H1,%H2\";
}"
[(set_attr "type" "insert_dword")])
[(set_attr "type" "insert")
(set_attr "size" "64")])
(define_insn "*insvdi_internal2"
[(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")

2
gcc/config/rs6000/rs64.md
View File

@ -46,7 +46,7 @@
"lsu_rs64")
(define_insn_reservation "rs64a-integer" 1
(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
(and (eq_attr "type" "integer,insert,shift,trap,\
var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "rs64a"))
"iu_rs64")

2
gcc/config/rs6000/titan.md
View File

@ -51,7 +51,7 @@
(define_bypass 2 "titan_mulhw" "titan_mulhw")
(define_insn_reservation "titan_fxu_shift_and_rotate" 2
(and (eq_attr "type" "insert_word,shift,var_shift_rotate,cntlz")
(and (eq_attr "type" "insert,shift,var_shift_rotate,cntlz")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing*2,titan_fxu_wb")