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[ARM/AArch64] Improve modeled latency between FP operations and FP->GP register moves

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* config/arm/cortex-a15-neon.md (cortex_a15_vfp_to_from_gp):
	Split into...
	(cortex_a15_gp_to_vfp): ...This.
	(cortex_a15_fp_to_gp): ...And this.
	Define and comment bypass from vfp operations to fp->gp moves.

From-SVN: r217725
This commit is contained in:
Kyrylo Tkachov 2014-11-18 16:26:02 +00:00 committed by Kyrylo Tkachov
parent 7b69b603ec
commit 58bd290e5b
2 changed files with 21 additions and 3 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2014-11-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/cortex-a15-neon.md (cortex_a15_vfp_to_from_gp):
Split into...
(cortex_a15_gp_to_vfp): ...This.
(cortex_a15_fp_to_gp): ...And this.
Define and comment bypass from vfp operations to fp->gp moves.
2014-11-18 Martin Liska <mliska@suse.cz>
* var-tracking.c (vt_find_locations): New fibonacci_node is used.

16
gcc/config/arm/cortex-a15-neon.md
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@ -655,10 +655,20 @@
(eq_attr "type" "fmov"))
"ca15_issue1,ca15_cx_perm")
(define_insn_reservation "cortex_a15_vfp_to_from_gp" 5
(define_insn_reservation "cortex_a15_gp_to_vfp" 5
(and (eq_attr "tune" "cortexa15")
(eq_attr "type" "f_mcr, f_mcrr, f_mrc, f_mrrc"))
"ca15_issue1,ca15_ls1+ca15_ls2")
(eq_attr "type" "f_mcr, f_mcrr"))
"ca15_issue1,ca15_ls")
(define_insn_reservation "cortex_a15_mov_vfp_to_gp" 5
(and (eq_attr "tune" "cortexa15")
(eq_attr "type" "f_mrc, f_mrrc"))
"ca15_issue1,ca15_ls")
;; Moves from floating point registers to general purpose registers
;; induce additional latency.
(define_bypass 10 "cortex_a15_vfp*, cortex_a15_neon*, cortex_a15_gp_to_vfp" "cortex_a15_mov_vfp_to_gp")
(define_insn_reservation "cortex_a15_vfp_ariths" 7
(and (eq_attr "tune" "cortexa15")