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Avoid 512-bit mode MOV for prefer-avx256 option in Intel AVX512 configuration
gcc/ * config/i386/i386.md(*movsf_internal, *movdf_internal): Avoid 512-bit AVX modes for TARGET_PREFER_AVX256. From-SVN: r254038
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@ -1,3 +1,8 @@
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2017-10-06 Sergey Shalnov <Sergey.Shalnov@intel.com>
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* config/i386/i386.md(*movsf_internal, *movdf_internal):
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Avoid 512-bit AVX modes for TARGET_PREFER_AVX256.
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2017-10-24 Eric Botcazou <ebotcazou@adacore.com>
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PR middle-end/82569
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@ -3575,8 +3575,10 @@
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/* movaps is one byte shorter for non-AVX targets. */
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(eq_attr "alternative" "13,17")
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(cond [(ior (match_operand 0 "ext_sse_reg_operand")
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(match_operand 1 "ext_sse_reg_operand"))
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(cond [(and (ior (not (match_test "TARGET_PREFER_AVX256"))
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(not (match_test "TARGET_AVX512VL")))
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(ior (match_operand 0 "ext_sse_reg_operand")
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(match_operand 1 "ext_sse_reg_operand")))
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(const_string "V8DF")
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(ior (not (match_test "TARGET_SSE2"))
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(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
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@ -3750,8 +3752,10 @@
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better to maintain the whole registers in single format
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to avoid problems on using packed logical operations. */
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(eq_attr "alternative" "6")
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(cond [(ior (match_operand 0 "ext_sse_reg_operand")
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(match_operand 1 "ext_sse_reg_operand"))
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(cond [(and (ior (not (match_test "TARGET_PREFER_AVX256"))
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(not (match_test "TARGET_AVX512VL")))
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(ior (match_operand 0 "ext_sse_reg_operand")
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(match_operand 1 "ext_sse_reg_operand")))
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(const_string "V16SF")
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(ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
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(match_test "TARGET_SSE_SPLIT_REGS"))
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