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Avoid 512-bit mode MOV for prefer-avx256 option in Intel AVX512 configuration

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gcc/
	* config/i386/i386.md(*movsf_internal, *movdf_internal):
	Avoid 512-bit AVX modes for TARGET_PREFER_AVX256.

From-SVN: r254038
This commit is contained in:
Sergey Shalnov 2017-10-24 10:34:55 +00:00 committed by Kirill Yukhin
parent bc2a7cebfd
commit 585a449d73
2 changed files with 13 additions and 4 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2017-10-06 Sergey Shalnov <Sergey.Shalnov@intel.com>
* config/i386/i386.md(*movsf_internal, *movdf_internal):
Avoid 512-bit AVX modes for TARGET_PREFER_AVX256.
2017-10-24 Eric Botcazou <ebotcazou@adacore.com>
PR middle-end/82569

12
gcc/config/i386/i386.md
View File

@ -3575,8 +3575,10 @@
/* movaps is one byte shorter for non-AVX targets. */
(eq_attr "alternative" "13,17")
(cond [(ior (match_operand 0 "ext_sse_reg_operand")
(match_operand 1 "ext_sse_reg_operand"))
(cond [(and (ior (not (match_test "TARGET_PREFER_AVX256"))
(not (match_test "TARGET_AVX512VL")))
(ior (match_operand 0 "ext_sse_reg_operand")
(match_operand 1 "ext_sse_reg_operand")))
(const_string "V8DF")
(ior (not (match_test "TARGET_SSE2"))
(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
@ -3750,8 +3752,10 @@
better to maintain the whole registers in single format
to avoid problems on using packed logical operations. */
(eq_attr "alternative" "6")
(cond [(ior (match_operand 0 "ext_sse_reg_operand")
(match_operand 1 "ext_sse_reg_operand"))
(cond [(and (ior (not (match_test "TARGET_PREFER_AVX256"))
(not (match_test "TARGET_AVX512VL")))
(ior (match_operand 0 "ext_sse_reg_operand")
(match_operand 1 "ext_sse_reg_operand")))
(const_string "V16SF")
(ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
(match_test "TARGET_SSE_SPLIT_REGS"))