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re PR target/40741 (code size explosion for integer comparison)

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2009-10-28  Paolo Bonzini  <bonzini@gnu.org>

	PR rtl-optimization/40741
	* config/arm/arm.c (thumb1_rtx_costs): IOR or XOR with
	a small constant is cheap.
	* config/arm/arm.md (andsi3, iorsi3): Try to place the result of
	force_reg on the LHS.
	(xorsi3): Likewise, and split the XOR if the constant is complex
	and not in Thumb mode.

2009-10-28  Paolo Bonzini  <bonzini@gnu.org>

	PR rtl-optimization/40741
	* gcc.target/arm/thumb-branch1.c: New.

From-SVN: r153650
This commit is contained in:
Paolo Bonzini 2009-10-28 10:17:29 +00:00 committed by Paolo Bonzini
parent 15e2a6c05e
commit 582021baa7
5 changed files with 69 additions and 8 deletions
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10
gcc/ChangeLog
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@ -1,3 +1,13 @@
2009-10-28 Paolo Bonzini <bonzini@gnu.org>
PR rtl-optimization/40741
* config/arm/arm.c (thumb1_rtx_costs): IOR or XOR with
a small constant is cheap.
* config/arm/arm.md (andsi3, iorsi3): Try to place the result of
force_reg on the LHS.
(xorsi3): Likewise, and split the XOR if the constant is complex
and not in Thumb mode.
2009-10-28 Paolo Bonzini <bonzini@gnu.org>
* expmed.c (emit_store_flag): Check costs before

2
gcc/config/arm/arm.c
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@ -6215,7 +6215,7 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
else if ((outer == PLUS || outer == COMPARE)
&& INTVAL (x) < 256 && INTVAL (x) > -256)
return 0;
else if (outer == AND
else if ((outer == IOR || outer == XOR || outer == AND)
&& INTVAL (x) < 256 && INTVAL (x) >= -256)
return COSTS_N_INSNS (1);
else if (outer == ASHIFT || outer == ASHIFTRT

49
gcc/config/arm/arm.md
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@ -1914,7 +1914,16 @@
else /* TARGET_THUMB1 */
{
if (GET_CODE (operands[2]) != CONST_INT)
operands[2] = force_reg (SImode, operands[2]);
{
rtx tmp = force_reg (SImode, operands[2]);
if (rtx_equal_p (operands[0], operands[1]))
operands[2] = tmp;
else
{
operands[2] = operands[1];
operands[1] = tmp;
}
}
else
{
int i;
@ -2623,7 +2632,16 @@
DONE;
}
else /* TARGET_THUMB1 */
operands [2] = force_reg (SImode, operands [2]);
{
rtx tmp = force_reg (SImode, operands[2]);
if (rtx_equal_p (operands[0], operands[1]))
operands[2] = tmp;
else
{
operands[2] = operands[1];
operands[1] = tmp;
}
}
}
"
)
@ -2731,12 +2749,29 @@
(define_expand "xorsi3"
[(set (match_operand:SI 0 "s_register_operand" "")
(xor:SI (match_operand:SI 1 "s_register_operand" "")
(match_operand:SI 2 "arm_rhs_operand" "")))]
(match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_EITHER"
"if (TARGET_THUMB1)
if (GET_CODE (operands[2]) == CONST_INT)
operands[2] = force_reg (SImode, operands[2]);
"
"if (GET_CODE (operands[2]) == CONST_INT)
{
if (TARGET_32BIT)
{
arm_split_constant (XOR, SImode, NULL_RTX,
INTVAL (operands[2]), operands[0], operands[1],
optimize && can_create_pseudo_p ());
DONE;
}
else /* TARGET_THUMB1 */
{
rtx tmp = force_reg (SImode, operands[2]);
if (rtx_equal_p (operands[0], operands[1]))
operands[2] = tmp;
else
{
operands[2] = operands[1];
operands[1] = tmp;
}
}
}"
)
(define_insn "*arm_xorsi3"

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2009-10-28 Paolo Bonzini <bonzini@gnu.org>
PR rtl-optimization/40741
* gcc.target/arm/thumb-branch1.c: New.
2009-10-27 Jason Merrill <jason@redhat.com>
* g++.dg/cpp0x/lambda/lambda-conv.C: New.

11
gcc/testsuite/gcc.target/arm/thumb-branch1.c Normal file
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@ -0,0 +1,11 @@
/* { dg-do compile } */
/* { dg-options "-Os -mthumb -march=armv5te" } */
int returnbool(int a, int b)
{
if (a < b)
return 1;
return 0;
}
/* { dg-final { scan-assembler-not "eor" } } */