mirror/gcc
2
0
Fork 0
mirror of git://gcc.gnu.org/git/gcc.git synced 2025-04-15 16:21:27 +08:00
Code Issues Packages Projects Releases Wiki Activity

re PR target/54892 (, ICE in extract_insn, at recog.c:2123)

Browse Source 
gcc/ChangeLog
	PR target/54892
	* config/arm/arm.c (arm_expand_compare_and_swap): Use SImode to make
	sure the mode is correct when falling through from above cases.

	gcc/testsuite/ChangeLog
	PR target/54892
	* gcc.target/arm/pr54892.c: New.

From-SVN: r192609
This commit is contained in:
Zhenqiang Chen 2012-10-19 09:24:39 +00:00 committed by Xuepeng Guo
parent c8379865b3
commit 57fc62cb32
4 changed files with 20 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2012-10-19 Zhenqiang Chen <zhenqiang.chen@linaro.org>
PR target/54892
* config/arm/arm.c (arm_expand_compare_and_swap): Use SImode to make
sure the mode is correct when falling through from above cases.
2012-10-19 Bin Cheng <bin.cheng@arm.com>
* common.opt (flag_ira_hoist_pressure): New.

4
gcc/config/arm/arm.c
View File

@ -25447,8 +25447,8 @@ arm_expand_compare_and_swap (rtx operands[])
case SImode:
/* Force the value into a register if needed. We waited until after
the zero-extension above to do this properly. */
if (!arm_add_operand (oldval, mode))
oldval = force_reg (mode, oldval);
if (!arm_add_operand (oldval, SImode))
oldval = force_reg (SImode, oldval);
break;
case DImode:

5
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2012-10-19 Zhenqiang Chen <zhenqiang.chen@linaro.org>
PR target/54892
* gcc.target/arm/pr54892.c: New.
2012-10-19 Bin Cheng <bin.cheng@arm.com>
* testsuite/gcc.dg/hoist-register-pressure.c: New test.

7
gcc/testsuite/gcc.target/arm/pr54892.c Normal file
View File

@ -0,0 +1,7 @@
/* { dg-do compile } */
int set_role(unsigned char role_id, short m_role)
{
return __sync_bool_compare_and_swap(&m_role, -1, role_id);
}