diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c349ff9dbdf..93351b8209a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
 Tue Oct 21 10:06:40 1997  Jeffrey A Law  (law@cygnus.com)
 
+	* mn10300.c (print_operand): Handle 'S'.
+	* mn10300.md (ashlsi3, lshrsi3, ashrsi3): Use %S for
+	shift amount in last alternative
+
 	* mn10300.c (expand_epilogue): Rework to handle register restores
 	in "ret" and "retf" instructions correctly.
 
diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c
index 7706061aa83..e5559212b07 100644
--- a/gcc/config/mn10300/mn10300.c
+++ b/gcc/config/mn10300/mn10300.c
@@ -254,6 +254,18 @@ print_operand (file, x, code)
 	output_address (GEN_INT ((~INTVAL (x)) & 0xff));
 	break;
 
+      /* For shift counts.  The hardware ignores the upper bits of
+	 any immediate, but the assembler will flag an out of range
+	 shift count as an error.  So we mask off the high bits
+	 of the immediate here.  */
+      case 'S':
+	if (GET_CODE (x) == CONST_INT)
+	  {
+	    fprintf (file, "%d", INTVAL (x) & 0x1f);
+	    break;
+	  }
+	/* FALL THROUGH */
+
       default:
 	switch (GET_CODE (x))
 	  {
diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md
index f821e499f2a..c835043c3f6 100644
--- a/gcc/config/mn10300/mn10300.md
+++ b/gcc/config/mn10300/mn10300.md
@@ -1269,7 +1269,7 @@
   asl2 %0
   asl2 %0\;add %0,%0
   asl2 %0\;asl2 %0
-  asl %2,%0"
+  asl %S2,%0"
   [(set_attr "cc" "set_zn")])
 
 (define_insn "lshrsi3"
@@ -1278,7 +1278,7 @@
 	 (match_operand:SI 1 "register_operand" "0")
 	 (match_operand:QI 2 "nonmemory_operand" "di")))]
   ""
-  "lsr %2,%0"
+  "lsr %S2,%0"
   [(set_attr "cc" "set_zn")])
 
 (define_insn "ashrsi3"
@@ -1287,7 +1287,7 @@
 	 (match_operand:SI 1 "register_operand" "0")
 	 (match_operand:QI 2 "nonmemory_operand" "di")))]
   ""
-  "asr %2,%0"
+  "asr %S2,%0"
   [(set_attr "cc" "set_zn")])
 
 ;; ----------------------------------------------------------------------