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mn10300.c (print_operand): Handle 'S'.

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* mn10300.c (print_operand): Handle 'S'.
        * mn10300.md (ashlsi3, lshrsi3, ashrsi3): Use %S for
        shift amount in last alternative

From-SVN: r16134
This commit is contained in:
Jeffrey A Law 1997-10-21 19:10:24 +00:00 committed by Jeff Law
parent 5d29a95f92
commit 576e5accbd
3 changed files with 19 additions and 3 deletions
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4
gcc/ChangeLog
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@ -1,5 +1,9 @@
Tue Oct 21 10:06:40 1997 Jeffrey A Law (law@cygnus.com)
* mn10300.c (print_operand): Handle 'S'.
* mn10300.md (ashlsi3, lshrsi3, ashrsi3): Use %S for
shift amount in last alternative
* mn10300.c (expand_epilogue): Rework to handle register restores
in "ret" and "retf" instructions correctly.

12
gcc/config/mn10300/mn10300.c
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@ -254,6 +254,18 @@ print_operand (file, x, code)
output_address (GEN_INT ((~INTVAL (x)) & 0xff));
break;
/* For shift counts. The hardware ignores the upper bits of
any immediate, but the assembler will flag an out of range
shift count as an error. So we mask off the high bits
of the immediate here. */
case 'S':
if (GET_CODE (x) == CONST_INT)
{
fprintf (file, "%d", INTVAL (x) & 0x1f);
break;
}
/* FALL THROUGH */
default:
switch (GET_CODE (x))
{

6
gcc/config/mn10300/mn10300.md
View File

@ -1269,7 +1269,7 @@
asl2 %0
asl2 %0\;add %0,%0
asl2 %0\;asl2 %0
asl %2,%0"
asl %S2,%0"
[(set_attr "cc" "set_zn")])
(define_insn "lshrsi3"
@ -1278,7 +1278,7 @@
(match_operand:SI 1 "register_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "di")))]
""
"lsr %2,%0"
"lsr %S2,%0"
[(set_attr "cc" "set_zn")])
(define_insn "ashrsi3"
@ -1287,7 +1287,7 @@
(match_operand:SI 1 "register_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "di")))]
""
"asr %2,%0"
"asr %S2,%0"
[(set_attr "cc" "set_zn")])
;; ----------------------------------------------------------------------