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docs: Document maskload else operand and behavior.
This patch amends the documentation for masked loads (maskload, vec_mask_load_lanes, and mask_gather_load as well as their len counterparts) with an else operand. gcc/ChangeLog: * doc/md.texi: Document masked load else operand.
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@ -5014,8 +5014,10 @@ This pattern is not allowed to @code{FAIL}.
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@item @samp{vec_mask_load_lanes@var{m}@var{n}}
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Like @samp{vec_load_lanes@var{m}@var{n}}, but takes an additional
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mask operand (operand 2) that specifies which elements of the destination
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vectors should be loaded. Other elements of the destination
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vectors are set to zero. The operation is equivalent to:
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vectors should be loaded. Other elements of the destination vectors are
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taken from operand 3, which is an else operand similar to the one in
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@code{maskload}.
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The operation is equivalent to:
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@smallexample
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int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
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@ -5025,7 +5027,7 @@ for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
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operand0[i][j] = operand1[j * c + i];
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else
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for (i = 0; i < c; i++)
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operand0[i][j] = 0;
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operand0[i][j] = operand3[j];
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@end smallexample
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This pattern is not allowed to @code{FAIL}.
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@ -5033,16 +5035,20 @@ This pattern is not allowed to @code{FAIL}.
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@cindex @code{vec_mask_len_load_lanes@var{m}@var{n}} instruction pattern
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@item @samp{vec_mask_len_load_lanes@var{m}@var{n}}
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Like @samp{vec_load_lanes@var{m}@var{n}}, but takes an additional
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mask operand (operand 2), length operand (operand 3) as well as bias operand (operand 4)
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that specifies which elements of the destination vectors should be loaded.
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Other elements of the destination vectors are undefined. The operation is equivalent to:
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mask operand (operand 2), length operand (operand 4) as well as bias operand
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(operand 5) that specifies which elements of the destination vectors should be
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loaded. Other elements of the destination vectors are taken from operand 3,
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which is an else operand similar to the one in @code{maskload}.
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The operation is equivalent to:
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@smallexample
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int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
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for (j = 0; j < operand3 + operand4; j++)
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if (operand2[j])
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for (i = 0; i < c; i++)
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for (j = 0; j < operand4 + operand5; j++)
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for (i = 0; i < c; i++)
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if (operand2[j])
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operand0[i][j] = operand1[j * c + i];
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else
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operand0[i][j] = operand3[j];
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@end smallexample
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This pattern is not allowed to @code{FAIL}.
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@ -5122,18 +5128,25 @@ address width.
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@cindex @code{mask_gather_load@var{m}@var{n}} instruction pattern
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@item @samp{mask_gather_load@var{m}@var{n}}
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Like @samp{gather_load@var{m}@var{n}}, but takes an extra mask operand as
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operand 5. Bit @var{i} of the mask is set if element @var{i}
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operand 5.
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Other elements of the destination vectors are taken from operand 6,
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which is an else operand similar to the one in @code{maskload}.
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Bit @var{i} of the mask is set if element @var{i}
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of the result should be loaded from memory and clear if element @var{i}
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of the result should be set to zero.
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of the result should be set to operand 6.
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@cindex @code{mask_len_gather_load@var{m}@var{n}} instruction pattern
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@item @samp{mask_len_gather_load@var{m}@var{n}}
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Like @samp{gather_load@var{m}@var{n}}, but takes an extra mask operand (operand 5),
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a len operand (operand 6) as well as a bias operand (operand 7). Similar to mask_len_load,
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the instruction loads at most (operand 6 + operand 7) elements from memory.
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Like @samp{gather_load@var{m}@var{n}}, but takes an extra mask operand
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(operand 5) and an else operand (operand 6) as well as a len operand
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(operand 7) and a bias operand (operand 8).
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Similar to mask_len_load the instruction loads at
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most (operand 7 + operand 8) elements from memory.
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Bit @var{i} of the mask is set if element @var{i} of the result should
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be loaded from memory and clear if element @var{i} of the result should be undefined.
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Mask elements @var{i} with @var{i} > (operand 6 + operand 7) are ignored.
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be loaded from memory and clear if element @var{i} of the result should
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be set to element @var{i} of operand 6.
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Mask elements @var{i} with @var{i} > (operand 7 + operand 8) are ignored.
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@cindex @code{mask_len_strided_load@var{m}} instruction pattern
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@item @samp{mask_len_strided_load@var{m}}
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@ -5392,8 +5405,13 @@ Operands 4 and 5 have a target-dependent scalar integer mode.
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@cindex @code{maskload@var{m}@var{n}} instruction pattern
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@item @samp{maskload@var{m}@var{n}}
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Perform a masked load of vector from memory operand 1 of mode @var{m}
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into register operand 0. Mask is provided in register operand 2 of
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mode @var{n}.
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into register operand 0. The mask is provided in register operand 2 of
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mode @var{n}. Operand 3 (the ``else value'') is of mode @var{m} and
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specifies which value is loaded when the mask is unset.
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The predicate of operand 3 must only accept the else values that the target
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actually supports. Currently three values are attempted, zero, -1, and
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undefined. GCC handles an else value of zero more efficiently than -1 or
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undefined.
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This pattern is not allowed to @code{FAIL}.
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@ -5459,15 +5477,16 @@ Operands 0 and 1 have mode @var{m}, which must be a vector mode. Operand 3
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has whichever integer mode the target prefers. A mask is specified in
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operand 2 which must be of type @var{n}. The mask has lower precedence than
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the length and is itself subject to length masking,
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i.e. only mask indices < (operand 3 + operand 4) are used.
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i.e. only mask indices < (operand 4 + operand 5) are used.
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Operand 3 is an else operand similar to the one in @code{maskload}.
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Operand 4 conceptually has mode @code{QI}.
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Operand 2 can be a variable or a constant amount. Operand 4 specifies a
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Operand 4 can be a variable or a constant amount. Operand 5 specifies a
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constant bias: it is either a constant 0 or a constant -1. The predicate on
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operand 4 must only accept the bias values that the target actually supports.
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operand 5 must only accept the bias values that the target actually supports.
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GCC handles a bias of 0 more efficiently than a bias of -1.
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If (operand 2 + operand 4) exceeds the number of elements in mode
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If (operand 4 + operand 5) exceeds the number of elements in mode
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@var{m}, the behavior is undefined.
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If the target prefers the length to be measured in bytes
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