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predicates.md (const_pow2_1_to_2_operand): Remove.
2011-05-09 Uros Bizjak <ubizjak@gmail.com>
* config/i386/predicates.md (const_pow2_1_to_2_operand): Remove.
(const_pow2_1_to_8_operand): Ditto.
(const_pow2_1_to_128_operand): Ditto.
(const_pow2_1_to_32768_operand): Ditto.
* config/i386/mmx.md (*mmx_pinsrw): Use const_int_operand instead of
const_pow2_1_to_8_operand for operand 3 predicate. Use exact_log2
in insn constraint to check integer value of operand 3.
* config/i386/sse.md (*vec_setv4sf_sse4_1): Ditto.
(PINSR_MODE): New mode iterator.
(sse2p4_1): New mode attribute.
(<sse2p4_1>_pinsr<ssemodesuffix>): Merge insn from sse4_1_pinsrb,
sse2_pinsrw, sse4_1_pinsrd and sse4_1_pinsrq using PINSR_MODE mode
iterator. Use const_int_operand instead of
const_pow2_1_to_{2,8,128,32768}_operand for operand 3 predicate. Use
exact_log2 in insn constraint to check integer value of operand 3.
2011-05-09 Uros Bizjak <ubizjak@gmail.com>
* config/i386/sse.md (blendbits): Remove mode attribute.
(<sse4_1>_blend<ssemodesuffix><avxsizesuffix>): Use const_int_operand
instead of const_0_to_<blendbits>_operand for operand 3 predicate.
Check integer value of operand 3 in insn constraint.
From-SVN: r173580
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
0ca8de87c4
commit
51e7f3770c
@ -1,3 +1,29 @@
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2011-05-09 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/predicates.md (const_pow2_1_to_2_operand): Remove.
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(const_pow2_1_to_8_operand): Ditto.
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(const_pow2_1_to_128_operand): Ditto.
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(const_pow2_1_to_32768_operand): Ditto.
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* config/i386/mmx.md (*mmx_pinsrw): Use const_int_operand instead of
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const_pow2_1_to_8_operand for operand 3 predicate. Use exact_log2
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in insn constraint to check integer value of operand 3.
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* config/i386/sse.md (*vec_setv4sf_sse4_1): Ditto.
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(PINSR_MODE): New mode iterator.
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(sse2p4_1): New mode attribute.
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(<sse2p4_1>_pinsr<ssemodesuffix>): Merge insn from sse4_1_pinsrb,
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sse2_pinsrw, sse4_1_pinsrd and sse4_1_pinsrq using PINSR_MODE mode
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iterator. Use const_int_operand instead of
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const_pow2_1_to_{2,8,128,32768}_operand for operand 3 predicate. Use
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exact_log2 in insn constraint to check integer value of operand 3.
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2011-05-09 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/sse.md (blendbits): Remove mode attribute.
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(<sse4_1>_blend<ssemodesuffix><avxsizesuffix>): Use const_int_operand
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instead of const_0_to_<blendbits>_operand for operand 3 predicate.
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Check integer value of operand 3 in insn constraint.
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2011-05-09 Richard Guenther <rguenther@suse.de>
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* lto-symtab.c (lto_cgraph_replace_node): Use types_compatible_p
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@ -1197,8 +1197,10 @@
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(vec_duplicate:V4HI
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(match_operand:HI 2 "nonimmediate_operand" "rm"))
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(match_operand:V4HI 1 "register_operand" "0")
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(match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
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"TARGET_SSE || TARGET_3DNOW_A"
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(match_operand:SI 3 "const_int_operand" "")))]
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"(TARGET_SSE || TARGET_3DNOW_A)
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&& ((unsigned) exact_log2 (INTVAL (operands[3]))
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< GET_MODE_NUNITS (V4HImode))"
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
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if (MEM_P (operands[2]))
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@ -688,36 +688,6 @@
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(and (match_code "const_int")
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(match_test "IN_RANGE (INTVAL (op), 12, 15)")))
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;; Match exactly one bit in 2-bit mask.
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(define_predicate "const_pow2_1_to_2_operand"
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(and (match_code "const_int")
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(ior (match_test "op == const1_rtx")
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(match_test "op == const2_rtx"))))
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;; Match exactly one bit in 4-bit mask.
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(define_predicate "const_pow2_1_to_8_operand"
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(match_code "const_int")
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{
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unsigned int log = exact_log2 (INTVAL (op));
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return log <= 3;
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})
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;; Match exactly one bit in 8-bit mask.
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(define_predicate "const_pow2_1_to_128_operand"
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(match_code "const_int")
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{
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unsigned int log = exact_log2 (INTVAL (op));
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return log <= 7;
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})
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;; Match exactly one bit in 16-bit mask.
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(define_predicate "const_pow2_1_to_32768_operand"
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(match_code "const_int")
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{
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unsigned int log = exact_log2 (INTVAL (op));
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return log <= 15;
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})
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;; True if this is a constant appropriate for an increment or decrement.
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(define_predicate "incdec_operand"
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(match_code "const_int")
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@ -178,10 +178,6 @@
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(define_mode_attr sserotatemax
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[(V16QI "7") (V8HI "15") (V4SI "31") (V2DI "63")])
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;; Mapping of immediate bits for blend instructions
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(define_mode_attr blendbits
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[(V8SF "255") (V4SF "15") (V4DF "15") (V2DF "3")])
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;; Instruction suffix for sign and zero extensions.
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(define_code_attr extsuffix [(sign_extend "sx") (zero_extend "zx")])
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@ -3337,7 +3333,7 @@
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[(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
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(set_attr "mode" "V4SF,SF,DI,DI")])
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(define_insn "*vec_concatv4sf_sse"
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(define_insn "*vec_concatv4sf"
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[(set (match_operand:V4SF 0 "register_operand" "=x,x,x,x")
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(vec_concat:V4SF
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(match_operand:V2SF 1 "register_operand" " 0,x,0,x")
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@ -3445,8 +3441,10 @@
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(vec_duplicate:V4SF
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(match_operand:SF 2 "nonimmediate_operand" "xm,xm"))
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(match_operand:V4SF 1 "register_operand" "0,x")
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(match_operand:SI 3 "const_pow2_1_to_8_operand" "n,n")))]
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"TARGET_SSE4_1"
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(match_operand:SI 3 "const_int_operand" "")))]
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"TARGET_SSE4_1
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&& ((unsigned) exact_log2 (INTVAL (operands[3]))
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< GET_MODE_NUNITS (V4SFmode))"
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])) << 4);
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switch (which_alternative)
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@ -6055,129 +6053,72 @@
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "TI")])
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(define_insn "sse4_1_pinsrb"
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[(set (match_operand:V16QI 0 "register_operand" "=x,x,x,x")
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(vec_merge:V16QI
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(vec_duplicate:V16QI
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(match_operand:QI 2 "nonimmediate_operand" "r,m,r,m"))
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(match_operand:V16QI 1 "register_operand" "0,0,x,x")
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(match_operand:SI 3 "const_pow2_1_to_32768_operand" "n,n,n,n")))]
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"TARGET_SSE4_1"
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;; Modes handled by pinsr patterns.
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(define_mode_iterator PINSR_MODE
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[(V16QI "TARGET_SSE4_1") V8HI
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(V4SI "TARGET_SSE4_1")
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(V2DI "TARGET_SSE4_1 && TARGET_64BIT")])
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(define_mode_attr sse2p4_1
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[(V16QI "sse4_1") (V8HI "sse2")
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(V4SI "sse4_1") (V2DI "sse4_1")])
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;; sse4_1_pinsrd must come before sse2_loadld since it is preferred.
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(define_insn "<sse2p4_1>_pinsr<ssemodesuffix>"
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[(set (match_operand:PINSR_MODE 0 "register_operand" "=x,x,x,x")
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(vec_merge:PINSR_MODE
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(vec_duplicate:PINSR_MODE
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(match_operand:<ssescalarmode> 2 "nonimmediate_operand" "r,m,r,m"))
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(match_operand:PINSR_MODE 1 "register_operand" "0,0,x,x")
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(match_operand:SI 3 "const_int_operand" "")))]
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"TARGET_SSE2
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&& ((unsigned) exact_log2 (INTVAL (operands[3]))
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< GET_MODE_NUNITS (<MODE>mode))"
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
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switch (which_alternative)
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{
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case 0:
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return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
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if (GET_MODE_SIZE (<ssescalarmode>mode) < GET_MODE_SIZE (SImode))
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return "pinsr<ssemodesuffix>\t{%3, %k2, %0|%0, %k2, %3}";
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/* FALLTHRU */
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case 1:
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return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
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return "pinsr<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}";
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case 2:
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return "vpinsrb\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
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if (GET_MODE_SIZE (<ssescalarmode>mode) < GET_MODE_SIZE (SImode))
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return "vpinsr<ssemodesuffix>\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
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/* FALLTHRU */
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case 3:
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return "vpinsrb\t{%3, %2, %1, %0|%0, %1, %2, %3}";
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return "vpinsr<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "isa" "noavx,noavx,avx,avx")
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(set_attr "type" "sselog")
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(set_attr "prefix_extra" "1")
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(set (attr "prefix_rex")
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(if_then_else
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(and (eq (symbol_ref "TARGET_AVX") (const_int 0))
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(eq (const_string "<MODE>mode") (const_string "V2DImode")))
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(const_string "1")
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(const_string "*")))
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(set (attr "prefix_data16")
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(if_then_else
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(and (eq (symbol_ref "TARGET_AVX") (const_int 0))
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(eq (const_string "<MODE>mode") (const_string "V8HImode")))
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(const_string "1")
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(const_string "*")))
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(set (attr "prefix_extra")
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(if_then_else
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(and (eq (symbol_ref "TARGET_AVX") (const_int 0))
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(eq (const_string "<MODE>mode") (const_string "V8HImode")))
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(const_string "*")
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(const_string "1")))
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "orig,orig,vex,vex")
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(set_attr "mode" "TI")])
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(define_insn "sse2_pinsrw"
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[(set (match_operand:V8HI 0 "register_operand" "=x,x,x,x")
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(vec_merge:V8HI
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(vec_duplicate:V8HI
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(match_operand:HI 2 "nonimmediate_operand" "r,m,r,m"))
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(match_operand:V8HI 1 "register_operand" "0,0,x,x")
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(match_operand:SI 3 "const_pow2_1_to_128_operand" "n,n,n,n")))]
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"TARGET_SSE2"
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
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switch (which_alternative)
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{
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case 0:
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return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
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case 1:
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return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
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case 2:
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return "vpinsrw\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
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case 3:
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return "vpinsrw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "isa" "noavx,noavx,avx,avx")
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(set_attr "type" "sselog")
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(set_attr "prefix_data16" "1,1,*,*")
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(set_attr "prefix_extra" "*,*,1,1")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "orig,orig,vex,vex")
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(set_attr "mode" "TI")])
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;; It must come before sse2_loadld since it is preferred.
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(define_insn "sse4_1_pinsrd"
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[(set (match_operand:V4SI 0 "register_operand" "=x,x")
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(vec_merge:V4SI
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(vec_duplicate:V4SI
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(match_operand:SI 2 "nonimmediate_operand" "rm,rm"))
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(match_operand:V4SI 1 "register_operand" "0,x")
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(match_operand:SI 3 "const_pow2_1_to_8_operand" "n,n")))]
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"TARGET_SSE4_1"
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
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switch (which_alternative)
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{
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case 0:
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return "pinsrd\t{%3, %2, %0|%0, %2, %3}";
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case 1:
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return "vpinsrd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sselog")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "TI")])
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(define_insn "sse4_1_pinsrq"
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[(set (match_operand:V2DI 0 "register_operand" "=x,x")
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(vec_merge:V2DI
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(vec_duplicate:V2DI
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(match_operand:DI 2 "nonimmediate_operand" "rm,rm"))
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(match_operand:V2DI 1 "register_operand" "0,x")
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(match_operand:SI 3 "const_pow2_1_to_2_operand" "n,n")))]
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"TARGET_SSE4_1 && TARGET_64BIT"
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
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switch (which_alternative)
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{
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case 0:
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return "pinsrq\t{%3, %2, %0|%0, %2, %3}";
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case 1:
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return "vpinsrq\t{%3, %2, %1, %0|%0, %1, %2, %3}";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "sselog")
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(set_attr "prefix_rex" "1,*")
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(set_attr "prefix_extra" "1")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "TI")])
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(define_insn "*sse4_1_pextrb_<mode>"
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[(set (match_operand:SWI48 0 "register_operand" "=r")
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(zero_extend:SWI48
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@ -7885,8 +7826,9 @@
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(vec_merge:VF
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(match_operand:VF 2 "nonimmediate_operand" "xm,xm")
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(match_operand:VF 1 "register_operand" "0,x")
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(match_operand:SI 3 "const_0_to_<blendbits>_operand" "n,n")))]
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"TARGET_SSE4_1"
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(match_operand:SI 3 "const_int_operand" "")))]
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"TARGET_SSE4_1
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&& IN_RANGE (INTVAL (operands[3]), 0, (1 << GET_MODE_NUNITS (<MODE>mode))-1)"
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"@
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blend<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
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vblend<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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