From 51b3f0773f84ef1e3aac56e687f67027c3fb070c Mon Sep 17 00:00:00 2001
From: James Greenhalgh <james.greenhalgh@arm.com>
Date: Tue, 16 Feb 2016 15:59:51 +0000
Subject: [PATCH] [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to
 FP_LO_REGS

gcc/

	* config/aarch64/aarch64.md
	(arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
	constraints for	operand 3.
	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.

From-SVN: r233460
---
 gcc/ChangeLog                      | 7 +++++++
 gcc/config/aarch64/aarch64-simd.md | 8 ++++----
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0fcc1ee73ee3..90d91a739bc4 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-02-16  James Greenhalgh  <james.greenhalgh@arm.com>
+
+	* config/aarch64/aarch64.md
+	(arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
+	constraints for	operand 3.
+	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
+
 2016-02-16  Jakub Jelinek  <jakub@redhat.com>
 	    Richard Biener  <rguenther@suse.de>
 
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 304784153115..d8497abdb515 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3240,7 +3240,7 @@
 	  [(match_operand:VDQHS 1 "register_operand" "0")
 	   (match_operand:VDQHS 2 "register_operand" "w")
 	   (vec_select:<VEL>
-	     (match_operand:<VCOND> 3 "register_operand" "w")
+	     (match_operand:<VCOND> 3 "register_operand" "<vwx>")
 	     (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
 	  SQRDMLH_AS))]
    "TARGET_SIMD_RDMA"
@@ -3258,7 +3258,7 @@
 	  [(match_operand:SD_HSI 1 "register_operand" "0")
 	   (match_operand:SD_HSI 2 "register_operand" "w")
 	   (vec_select:<VEL>
-	     (match_operand:<VCOND> 3 "register_operand" "w")
+	     (match_operand:<VCOND> 3 "register_operand" "<vwx>")
 	     (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
 	  SQRDMLH_AS))]
    "TARGET_SIMD_RDMA"
@@ -3278,7 +3278,7 @@
 	  [(match_operand:VDQHS 1 "register_operand" "0")
 	   (match_operand:VDQHS 2 "register_operand" "w")
 	   (vec_select:<VEL>
-	     (match_operand:<VCONQ> 3 "register_operand" "w")
+	     (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
 	     (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
 	  SQRDMLH_AS))]
    "TARGET_SIMD_RDMA"
@@ -3296,7 +3296,7 @@
 	  [(match_operand:SD_HSI 1 "register_operand" "0")
 	   (match_operand:SD_HSI 2 "register_operand" "w")
 	   (vec_select:<VEL>
-	     (match_operand:<VCONQ> 3 "register_operand" "w")
+	     (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
 	     (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
 	  SQRDMLH_AS))]
    "TARGET_SIMD_RDMA"