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[Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS

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gcc/

	* config/aarch64/aarch64.md
	(arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
	constraints for	operand 3.
	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.

From-SVN: r233460
This commit is contained in:
James Greenhalgh 2016-02-16 15:59:51 +00:00 committed by James Greenhalgh
parent e387d491ab
commit 51b3f0773f
2 changed files with 11 additions and 4 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2016-02-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md
(arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
constraints for operand 3.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
2016-02-16 Jakub Jelinek <jakub@redhat.com>
Richard Biener <rguenther@suse.de>

8
gcc/config/aarch64/aarch64-simd.md
View File

@ -3240,7 +3240,7 @@
[(match_operand:VDQHS 1 "register_operand" "0")
(match_operand:VDQHS 2 "register_operand" "w")
(vec_select:<VEL>
(match_operand:<VCOND> 3 "register_operand" "w")
(match_operand:<VCOND> 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
@ -3258,7 +3258,7 @@
[(match_operand:SD_HSI 1 "register_operand" "0")
(match_operand:SD_HSI 2 "register_operand" "w")
(vec_select:<VEL>
(match_operand:<VCOND> 3 "register_operand" "w")
(match_operand:<VCOND> 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
@ -3278,7 +3278,7 @@
[(match_operand:VDQHS 1 "register_operand" "0")
(match_operand:VDQHS 2 "register_operand" "w")
(vec_select:<VEL>
(match_operand:<VCONQ> 3 "register_operand" "w")
(match_operand:<VCONQ> 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"
@ -3296,7 +3296,7 @@
[(match_operand:SD_HSI 1 "register_operand" "0")
(match_operand:SD_HSI 2 "register_operand" "w")
(vec_select:<VEL>
(match_operand:<VCONQ> 3 "register_operand" "w")
(match_operand:<VCONQ> 3 "register_operand" "<vwx>")
(parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
SQRDMLH_AS))]
"TARGET_SIMD_RDMA"