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Add post-reload splitter for extendditi2 on x86_64.
This is another step towards a possible solution for PR 105137.
This patch introduces a define_insn for extendditi2 that allows
DImode to TImode sign-extension to be represented in the early
RTL optimizers, before being split post-reload into the exact
same idiom as currently produced by RTL expansion.
Typically this produces the identical code, so the first new
test case:
__int128 foo(long long x) { return (__int128)x; }
continues to generate:
foo: movq %rdi, %rax
cqto
ret
The "magic" is that this representation allows combine and the
other RTL optimizers to do a better job. Hence, the second
test case:
__int128 foo(__int128 a, long long b) {
a += ((__int128)b) << 70;
return a;
}
which mainline with -O2 currently generates as:
foo: movq %rsi, %rax
movq %rdx, %rcx
movq %rdi, %rsi
salq $6, %rcx
movq %rax, %rdi
xorl %eax, %eax
movq %rcx, %rdx
addq %rsi, %rax
adcq %rdi, %rdx
ret
with this patch now becomes:
foo: movl $0, %eax
salq $6, %rdx
addq %rdi, %rax
adcq %rsi, %rdx
ret
i.e. the same code for the signed and unsigned extension variants.
2023-01-01 Roger Sayle <roger@nextmovesoftware.com>
Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog
* config/i386/i386.md (extendditi2): New define_insn.
(define_split): Use DWIH mode iterator to treat new extendditi2
identically to existing extendsidi2_1.
(define_peephole2): Likewise.
(define_peephole2): Likewise.
(define_Split): Likewise.
gcc/testsuite/ChangeLog
* gcc.target/i386/extendditi2-1.c: New test case.
* gcc.target/i386/extendditi2-2.c: Likewise.
This commit is contained in:
Roger Sayle
parent
d64f877906
commit
4f1314f547
@ -4548,17 +4548,27 @@
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"!TARGET_64BIT"
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"#")
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(define_insn "extendditi2"
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[(set (match_operand:TI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
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(sign_extend:TI (match_operand:DI 1 "register_operand" "0,0,r,r")))
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(clobber (reg:CC FLAGS_REG))
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(clobber (match_scratch:DI 2 "=X,X,X,&r"))]
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"TARGET_64BIT"
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"#")
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;; Split the memory case. If the source register doesn't die, it will stay
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;; this way, if it does die, following peephole2s take care of it.
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(define_split
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[(set (match_operand:DI 0 "memory_operand")
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(sign_extend:DI (match_operand:SI 1 "register_operand")))
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[(set (match_operand:<DWI> 0 "memory_operand")
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(sign_extend:<DWI> (match_operand:DWIH 1 "register_operand")))
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(clobber (reg:CC FLAGS_REG))
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(clobber (match_operand:SI 2 "register_operand"))]
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(clobber (match_operand:DWIH 2 "register_operand"))]
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"reload_completed"
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[(const_int 0)]
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{
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split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);
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rtx bits = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT - 1);
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split_double_mode (<DWI>mode, &operands[0], 1, &operands[3], &operands[4]);
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emit_move_insn (operands[3], operands[1]);
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@ -4567,12 +4577,12 @@
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&& REGNO (operands[1]) == AX_REG
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&& REGNO (operands[2]) == DX_REG)
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{
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emit_insn (gen_ashrsi3_cvt (operands[2], operands[1], GEN_INT (31)));
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emit_insn (gen_ashr<mode>3_cvt (operands[2], operands[1], bits));
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}
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else
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{
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emit_move_insn (operands[2], operands[1]);
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emit_insn (gen_ashrsi3_cvt (operands[2], operands[2], GEN_INT (31)));
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emit_insn (gen_ashr<mode>3_cvt (operands[2], operands[2], bits));
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}
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emit_move_insn (operands[4], operands[2]);
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DONE;
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@ -4581,69 +4591,79 @@
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;; Peepholes for the case where the source register does die, after
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;; being split with the above splitter.
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(define_peephole2
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[(set (match_operand:SI 0 "memory_operand")
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(match_operand:SI 1 "general_reg_operand"))
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(set (match_operand:SI 2 "general_reg_operand") (match_dup 1))
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[(set (match_operand:DWIH 0 "memory_operand")
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(match_operand:DWIH 1 "general_reg_operand"))
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(set (match_operand:DWIH 2 "general_reg_operand") (match_dup 1))
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(parallel [(set (match_dup 2)
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(ashiftrt:SI (match_dup 2) (const_int 31)))
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(ashiftrt:DWIH (match_dup 2)
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(match_operand 4 "const_int_operand")))
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(clobber (reg:CC FLAGS_REG))])
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(set (match_operand:SI 3 "memory_operand") (match_dup 2))]
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(set (match_operand:DWIH 3 "memory_operand") (match_dup 2))]
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"REGNO (operands[1]) != REGNO (operands[2])
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&& INTVAL (operands[4]) == (<MODE_SIZE> * BITS_PER_UNIT - 1)
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&& peep2_reg_dead_p (2, operands[1])
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&& peep2_reg_dead_p (4, operands[2])
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&& !reg_mentioned_p (operands[2], operands[3])"
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[(set (match_dup 0) (match_dup 1))
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(parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
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(parallel [(set (match_dup 1) (ashiftrt:DWIH (match_dup 1) (match_dup 4)))
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(clobber (reg:CC FLAGS_REG))])
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(set (match_dup 3) (match_dup 1))])
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(define_peephole2
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[(set (match_operand:SI 0 "memory_operand")
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(match_operand:SI 1 "general_reg_operand"))
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(parallel [(set (match_operand:SI 2 "general_reg_operand")
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(ashiftrt:SI (match_dup 1) (const_int 31)))
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[(set (match_operand:DWIH 0 "memory_operand")
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(match_operand:DWIH 1 "general_reg_operand"))
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(parallel [(set (match_operand:DWIH 2 "general_reg_operand")
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(ashiftrt:DWIH (match_dup 1)
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(match_operand 4 "const_int_operand")))
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(clobber (reg:CC FLAGS_REG))])
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(set (match_operand:SI 3 "memory_operand") (match_dup 2))]
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(set (match_operand:DWIH 3 "memory_operand") (match_dup 2))]
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"/* cltd is shorter than sarl $31, %eax */
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!optimize_function_for_size_p (cfun)
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&& REGNO (operands[1]) == AX_REG
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&& REGNO (operands[2]) == DX_REG
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&& INTVAL (operands[4]) == (<MODE_SIZE> * BITS_PER_UNIT - 1)
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&& peep2_reg_dead_p (2, operands[1])
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&& peep2_reg_dead_p (3, operands[2])
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&& !reg_mentioned_p (operands[2], operands[3])"
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[(set (match_dup 0) (match_dup 1))
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(parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
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(parallel [(set (match_dup 1) (ashiftrt:DWIH (match_dup 1) (match_dup 4)))
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(clobber (reg:CC FLAGS_REG))])
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(set (match_dup 3) (match_dup 1))])
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;; Extend to register case. Optimize case where source and destination
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;; registers match and cases where we can use cltd.
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(sign_extend:DI (match_operand:SI 1 "register_operand")))
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[(set (match_operand:<DWI> 0 "register_operand")
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(sign_extend:<DWI> (match_operand:DWIH 1 "register_operand")))
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(clobber (reg:CC FLAGS_REG))
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(clobber (match_scratch:SI 2))]
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(clobber (match_scratch:DWIH 2))]
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"reload_completed"
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[(const_int 0)]
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{
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split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);
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rtx bits = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT - 1);
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split_double_mode (<DWI>mode, &operands[0], 1, &operands[3], &operands[4]);
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if (REGNO (operands[3]) != REGNO (operands[1]))
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emit_move_insn (operands[3], operands[1]);
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rtx src = operands[1];
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if (REGNO (operands[3]) == AX_REG)
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src = operands[3];
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/* Generate a cltd if possible and doing so it profitable. */
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if ((optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)
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&& REGNO (operands[3]) == AX_REG
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&& REGNO (src) == AX_REG
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&& REGNO (operands[4]) == DX_REG)
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{
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emit_insn (gen_ashrsi3_cvt (operands[4], operands[3], GEN_INT (31)));
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emit_insn (gen_ashr<mode>3_cvt (operands[4], src, bits));
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DONE;
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}
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if (REGNO (operands[4]) != REGNO (operands[1]))
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emit_move_insn (operands[4], operands[1]);
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emit_insn (gen_ashrsi3_cvt (operands[4], operands[4], GEN_INT (31)));
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emit_insn (gen_ashr<mode>3_cvt (operands[4], operands[4], bits));
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DONE;
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})
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8
gcc/testsuite/gcc.target/i386/extendditi2-1.c
Normal file
8
gcc/testsuite/gcc.target/i386/extendditi2-1.c
Normal file
@ -0,0 +1,8 @@
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/* { dg-do compile { target int128 } } */
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/* { dg-options "-O2" } */
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__int128 foo(long long x)
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{
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return (__int128)x;
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}
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/* { dg-final { scan-assembler "cqt?o" } } */
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13
gcc/testsuite/gcc.target/i386/extendditi2-2.c
Normal file
13
gcc/testsuite/gcc.target/i386/extendditi2-2.c
Normal file
@ -0,0 +1,13 @@
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/* { dg-do compile { target int128 } } */
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/* { dg-options "-O2" } */
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__int128 foo(__int128 a, long long b) {
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a += ((__int128)b) << 70;
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return a;
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}
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__int128 bar(__int128 a, unsigned long long b) {
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a += ((__int128)b) << 70;
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return a;
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}
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/* { dg-final { scan-assembler-not "movq" } } */
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