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Support AVX Programming Reference (June, 2010).
gcc/ 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * config/i386/cpuid.h (bit_F16C): New. (bit_RDRND): Likewise. (bit_FSGSBASE): Likewise. * config/i386/i386-builtin-types.def: Add "DEF_FUNCTION_TYPE (UINT16)", function types for float16 <-> float conversions and "DEF_FUNCTION_TYPE (VOID, UINT64)". * config/i386/i386-c.c (ix86_target_macros_internal): Support OPTION_MASK_ISA_FSGSBASE, OPTION_MASK_ISA_RDRND and OPTION_MASK_ISA_F16C. * config/i386/i386.c (OPTION_MASK_ISA_FSGSBASE_SET): New. (OPTION_MASK_ISA_RDRND_SET): Likewise. (OPTION_MASK_ISA_F16C_SET): Likewise. (OPTION_MASK_ISA_FSGSBASE_UNSET): Likewise. (OPTION_MASK_ISA_RDRND_UNSET): Likewise. (OPTION_MASK_ISA_F16C_UNSET): Likewise. (OPTION_MASK_ISA_AVX_UNSET): Add OPTION_MASK_ISA_F16C_UNSET. (ix86_handle_option): Handle OPT_mfsgsbase, OPT_mrdrnd and OPT_mf16c. (ix86_target_string): Support -mfsgsbase, -mrdrnd and -mf16c. (pta_flags): Add PTA_FSGSBASE, PTA_RDRND and PTA_F16C. (override_options): Handle them. (ix86_valid_target_attribute_inner_p): Handle fsgsbase, rdrnd and f16c. (ix86_builtins): Add IX86_BUILTIN_RDFSBASE32, IX86_BUILTIN_RDFSBASE64, IX86_BUILTIN_RDGSBASE32, IX86_BUILTIN_RDGSBASE64, IX86_BUILTIN_WRFSBASE32, IX86_BUILTIN_WRFSBASE64, IX86_BUILTIN_WRGSBASE32, IX86_BUILTIN_WRGSBASE64, IX86_BUILTIN_RDRAND16, IX86_BUILTIN_RDRAND32, IX86_BUILTIN_RDRAND64, IX86_BUILTIN_CVTPH2PS, IX86_BUILTIN_CVTPH2PS256, IX86_BUILTIN_CVTPS2PH and IX86_BUILTIN_CVTPS2PH256. (bdesc_args): Likewise. (ix86_expand_args_builtin): Handle V8SF_FTYPE_V8HI, V4SF_FTYPE_V8HI, V8HI_FTYPE_V8SF_INT and V8HI_FTYPE_V4SF_INT. (ix86_expand_special_args_builtin): Handle VOID_FTYPE_UINT64, VOID_FTYPE_UNSIGNED, UNSIGNED_FTYPE_VOID and UINT16_FTYPE_VOID. Handle non-memory store. * config/i386/i386.h (TARGET_FSGSBASE): New. (TARGET_RDRND): Likewise. (TARGET_F12C): Likewise. * config/i386/i386.md (UNSPEC_VCVTPH2PS): New. (UNSPEC_VCVTPS2PH): Likewise. (UNSPECV_RDFSBASE): Likewise. (UNSPECV_RDGSBASE): Likewise. (UNSPECV_WRFSBASE): Likewise. (UNSPECV_WRGSBASE): Likewise. (UNSPECV_RDRAND): Likewise. (rdfsbase<mode>): Likewise. (rdgsbase<mode>): Likewise. (wrfsbase<mode>): Likewise. (wrgsbase<mode>): Likewise. (rdrand<mode>): Likewise. * config/i386/i386.opt: Add -mfsgsbase, -mrdrnd and -mf16c. * config/i386/immintrin.h (_rdrand_u16): New. (_rdrand_u32): Likewise. (_readfsbase_u32): Likewise. (_readfsbase_u64): Likewise. (_readgsbase_u32): Likewise. (_readgsbase_u64): Likewise. (_writefsbase_u32): Likewise. (_writefsbase_u64): Likewise. (_writegsbase_u32): Likewise. (_writegsbase_u64): Likewise. (_rdrand_u64): Likewise. (_cvtsh_ss): Likewise. (_mm_cvtph_ps): Likewise. (_mm256_cvtph_ps): Likewise. (_cvtss_sh): Likewise. (_mm_cvtps_ph): Likewise. (_mm256_cvtps_ph): Likewise. * config/i386/sse.md (vcvtph2ps): New. (*vcvtph2ps_load): Likewise. (vcvtph2ps256): Likewise. (vcvtps2ph): Likewise. (*vcvtps2ph): Likewise. (*vcvtps2ph_store): Likewise. (vcvtps2ph256): Likewise. * doc/extend.texi: Document FSGSBASE and RDRND built-in functions. * doc/invoke.texi: Document -mfsgsbase, -mrdrnd and -mf16c. gcc/testsuite/ 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * g++.dg/other/i386-2.C: Add -mfsgsbase -mrdrnd -mf16c. * g++.dg/other/i386-3.C: Likewise. * gcc.target/i386/sse-12.c: Likewise. * gcc.target/i386/f16c-check.h: New. * gcc.target/i386/rdfsbase-1.c: Likewise. * gcc.target/i386/rdfsbase-2.c: Likewise. * gcc.target/i386/rdgsbase-1.c: Likewise. * gcc.target/i386/rdgsbase-2.c: Likewise. * gcc.target/i386/rdrand-1.c: Likewise. * gcc.target/i386/rdrand-2.c: Likewise. * gcc.target/i386/rdrand-3.c: Likewise. * gcc.target/i386/vcvtph2ps-1.c: Likewise. * gcc.target/i386/vcvtph2ps-2.c: Likewise. * gcc.target/i386/vcvtph2ps-3.c: Likewise. * gcc.target/i386/vcvtps2ph-1.c: Likewise. * gcc.target/i386/vcvtps2ph-2.c: Likewise. * gcc.target/i386/vcvtps2ph-3.c: Likewise. * gcc.target/i386/wrfsbase-1.c: Likewise. * gcc.target/i386/wrfsbase-2.c: Likewise. * gcc.target/i386/wrgsbase-1.c: Likewise. * gcc.target/i386/wrgsbase-2.c: Likewise. * gcc.target/i386/sse-13.c: Add -mfsgsbase -mrdrnd -mf16c. (__builtin_ia32_vcvtps2ph): New. (__builtin_ia32_vcvtps2ph256): Likewise. * gcc.target/i386/sse-14.c: Add -mfsgsbase -mrdrnd -mf16c. Test _cvtss_sh, _mm_cvtps_ph and _mm256_cvtps_ph. * gcc.target/i386/sse-22.c: Add fsgsbase,rdrnd,f16c. Test _cvtss_sh, _mm_cvtps_ph and _mm256_cvtps_ph. * gcc.target/i386/sse-23.c (__builtin_ia32_vcvtps2ph): New. (__builtin_ia32_vcvtps2ph256): Likewise. Add fsgsbase,rdrnd,f16c. * lib/target-supports.exp (check_effective_target_f16c): New. From-SVN: r161855
This commit is contained in:
H.J. Lu
H.J. Lu
parent
9e6d8a0d27
commit
4ee89d5fb7
@ -1,3 +1,97 @@
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2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
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AVX Programming Reference (June, 2010)
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* config/i386/cpuid.h (bit_F16C): New.
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(bit_RDRND): Likewise.
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(bit_FSGSBASE): Likewise.
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* config/i386/i386-builtin-types.def: Add
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"DEF_FUNCTION_TYPE (UINT16)", function types for
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float16 <-> float conversions and
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"DEF_FUNCTION_TYPE (VOID, UINT64)".
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* config/i386/i386-c.c (ix86_target_macros_internal): Support
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OPTION_MASK_ISA_FSGSBASE, OPTION_MASK_ISA_RDRND and
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OPTION_MASK_ISA_F16C.
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* config/i386/i386.c (OPTION_MASK_ISA_FSGSBASE_SET): New.
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(OPTION_MASK_ISA_RDRND_SET): Likewise.
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(OPTION_MASK_ISA_F16C_SET): Likewise.
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(OPTION_MASK_ISA_FSGSBASE_UNSET): Likewise.
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(OPTION_MASK_ISA_RDRND_UNSET): Likewise.
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(OPTION_MASK_ISA_F16C_UNSET): Likewise.
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(OPTION_MASK_ISA_AVX_UNSET): Add OPTION_MASK_ISA_F16C_UNSET.
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(ix86_handle_option): Handle OPT_mfsgsbase, OPT_mrdrnd and
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OPT_mf16c.
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(ix86_target_string): Support -mfsgsbase, -mrdrnd and -mf16c.
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(pta_flags): Add PTA_FSGSBASE, PTA_RDRND and PTA_F16C.
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(override_options): Handle them.
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(ix86_valid_target_attribute_inner_p): Handle fsgsbase, rdrnd
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and f16c.
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(ix86_builtins): Add IX86_BUILTIN_RDFSBASE32,
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IX86_BUILTIN_RDFSBASE64, IX86_BUILTIN_RDGSBASE32,
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IX86_BUILTIN_RDGSBASE64, IX86_BUILTIN_WRFSBASE32,
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IX86_BUILTIN_WRFSBASE64, IX86_BUILTIN_WRGSBASE32,
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IX86_BUILTIN_WRGSBASE64, IX86_BUILTIN_RDRAND16,
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IX86_BUILTIN_RDRAND32, IX86_BUILTIN_RDRAND64,
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IX86_BUILTIN_CVTPH2PS, IX86_BUILTIN_CVTPH2PS256,
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IX86_BUILTIN_CVTPS2PH and IX86_BUILTIN_CVTPS2PH256.
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(bdesc_args): Likewise.
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(ix86_expand_args_builtin): Handle V8SF_FTYPE_V8HI,
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V4SF_FTYPE_V8HI, V8HI_FTYPE_V8SF_INT and V8HI_FTYPE_V4SF_INT.
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(ix86_expand_special_args_builtin): Handle VOID_FTYPE_UINT64,
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VOID_FTYPE_UNSIGNED, UNSIGNED_FTYPE_VOID and UINT16_FTYPE_VOID.
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Handle non-memory store.
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* config/i386/i386.h (TARGET_FSGSBASE): New.
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(TARGET_RDRND): Likewise.
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(TARGET_F12C): Likewise.
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* config/i386/i386.md (UNSPEC_VCVTPH2PS): New.
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(UNSPEC_VCVTPS2PH): Likewise.
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(UNSPECV_RDFSBASE): Likewise.
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(UNSPECV_RDGSBASE): Likewise.
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(UNSPECV_WRFSBASE): Likewise.
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(UNSPECV_WRGSBASE): Likewise.
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(UNSPECV_RDRAND): Likewise.
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(rdfsbase<mode>): Likewise.
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(rdgsbase<mode>): Likewise.
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(wrfsbase<mode>): Likewise.
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(wrgsbase<mode>): Likewise.
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(rdrand<mode>): Likewise.
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* config/i386/i386.opt: Add -mfsgsbase, -mrdrnd and -mf16c.
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* config/i386/immintrin.h (_rdrand_u16): New.
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(_rdrand_u32): Likewise.
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(_readfsbase_u32): Likewise.
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(_readfsbase_u64): Likewise.
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(_readgsbase_u32): Likewise.
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(_readgsbase_u64): Likewise.
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(_writefsbase_u32): Likewise.
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(_writefsbase_u64): Likewise.
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(_writegsbase_u32): Likewise.
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(_writegsbase_u64): Likewise.
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(_rdrand_u64): Likewise.
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(_cvtsh_ss): Likewise.
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(_mm_cvtph_ps): Likewise.
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(_mm256_cvtph_ps): Likewise.
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(_cvtss_sh): Likewise.
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(_mm_cvtps_ph): Likewise.
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(_mm256_cvtps_ph): Likewise.
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* config/i386/sse.md (vcvtph2ps): New.
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(*vcvtph2ps_load): Likewise.
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(vcvtph2ps256): Likewise.
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(vcvtps2ph): Likewise.
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(*vcvtps2ph): Likewise.
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(*vcvtps2ph_store): Likewise.
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(vcvtps2ph256): Likewise.
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* doc/extend.texi: Document FSGSBASE and RDRND built-in functions.
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* doc/invoke.texi: Document -mfsgsbase, -mrdrnd and -mf16c.
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2010-07-05 Joern Rennecke <joern.rennecke@embecosm.com>
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PR bootstrap/44512
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@ -35,6 +35,8 @@
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#define bit_XSAVE (1 << 26)
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#define bit_OSXSAVE (1 << 27)
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#define bit_AVX (1 << 28)
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#define bit_F16C (1 << 29)
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#define bit_RDRND (1 << 30)
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/* %edx */
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#define bit_CMPXCHG8B (1 << 8)
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@ -58,6 +60,8 @@
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#define bit_3DNOWP (1 << 30)
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#define bit_3DNOW (1 << 31)
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/* Extended Features (%eax == 7) */
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#define bit_FSGSBASE (1 << 0)
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#if defined(__i386__) && defined(__PIC__)
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/* %ebx may be the PIC register. */
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@ -128,6 +128,7 @@ DEF_POINTER_TYPE (PCV8SF, V8SF, CONST)
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DEF_FUNCTION_TYPE (FLOAT128)
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DEF_FUNCTION_TYPE (UINT64)
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DEF_FUNCTION_TYPE (UNSIGNED)
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DEF_FUNCTION_TYPE (UINT16)
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DEF_FUNCTION_TYPE (VOID)
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DEF_FUNCTION_TYPE (PVOID)
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@ -179,6 +180,7 @@ DEF_FUNCTION_TYPE (V4SF, V4DF)
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DEF_FUNCTION_TYPE (V4SF, V4SF)
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DEF_FUNCTION_TYPE (V4SF, V4SI)
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DEF_FUNCTION_TYPE (V4SF, V8SF)
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DEF_FUNCTION_TYPE (V4SF, V8HI)
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DEF_FUNCTION_TYPE (V4SI, V16QI)
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DEF_FUNCTION_TYPE (V4SI, V2DF)
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DEF_FUNCTION_TYPE (V4SI, V4DF)
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@ -194,10 +196,12 @@ DEF_FUNCTION_TYPE (V8SF, PCV4SF)
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DEF_FUNCTION_TYPE (V8SF, V4SF)
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DEF_FUNCTION_TYPE (V8SF, V8SF)
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DEF_FUNCTION_TYPE (V8SF, V8SI)
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DEF_FUNCTION_TYPE (V8SF, V8HI)
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DEF_FUNCTION_TYPE (V8SI, V4SI)
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DEF_FUNCTION_TYPE (V8SI, V8SF)
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DEF_FUNCTION_TYPE (VOID, PCVOID)
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DEF_FUNCTION_TYPE (VOID, PVOID)
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DEF_FUNCTION_TYPE (VOID, UINT64)
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DEF_FUNCTION_TYPE (VOID, UNSIGNED)
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DEF_FUNCTION_TYPE (DI, V2DI, INT)
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@ -282,6 +286,8 @@ DEF_FUNCTION_TYPE (V8HI, V4SI, V4SI)
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DEF_FUNCTION_TYPE (V8HI, V8HI, INT)
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DEF_FUNCTION_TYPE (V8HI, V8HI, SI)
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DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI)
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DEF_FUNCTION_TYPE (V8HI, V8SF, INT)
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DEF_FUNCTION_TYPE (V8HI, V4SF, INT)
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DEF_FUNCTION_TYPE (V8QI, V4HI, V4HI)
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DEF_FUNCTION_TYPE (V8QI, V8QI, V8QI)
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DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SF)
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@ -246,6 +246,12 @@ ix86_target_macros_internal (int isa_flag,
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def_or_undef (parse_in, "__ABM__");
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if (isa_flag & OPTION_MASK_ISA_POPCNT)
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def_or_undef (parse_in, "__POPCNT__");
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if (isa_flag & OPTION_MASK_ISA_FSGSBASE)
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def_or_undef (parse_in, "__FSGSBASE__");
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if (isa_flag & OPTION_MASK_ISA_RDRND)
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def_or_undef (parse_in, "__RDRND__");
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if (isa_flag & OPTION_MASK_ISA_F16C)
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def_or_undef (parse_in, "__F16C__");
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if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE))
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def_or_undef (parse_in, "__SSE_MATH__");
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if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE2))
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@ -2081,6 +2081,11 @@ static int ix86_isa_flags_explicit;
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#define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
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#define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
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#define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
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#define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
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#define OPTION_MASK_ISA_F16C_SET \
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(OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
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/* Define a set of ISAs which aren't available when a given ISA is
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disabled. MMX and SSE ISAs are handled separately. */
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@ -2106,7 +2111,7 @@ static int ix86_isa_flags_explicit;
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(OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
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#define OPTION_MASK_ISA_AVX_UNSET \
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(OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
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| OPTION_MASK_ISA_FMA4_UNSET)
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| OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET)
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#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
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/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
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@ -2130,6 +2135,10 @@ static int ix86_isa_flags_explicit;
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#define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
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#define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
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#define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
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#define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
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#define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
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/* Vectorization library interface and handlers. */
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tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
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static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
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@ -2499,6 +2508,45 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
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}
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return true;
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case OPT_mfsgsbase:
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if (value)
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{
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ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
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ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
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}
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else
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{
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ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
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ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
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}
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return true;
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case OPT_mrdrnd:
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if (value)
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{
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ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
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ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
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}
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else
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{
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ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
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ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
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}
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return true;
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case OPT_mf16c:
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if (value)
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{
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ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
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ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
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}
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else
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{
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ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
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ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
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}
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return true;
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default:
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return true;
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}
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@ -2542,6 +2590,9 @@ ix86_target_string (int isa, int flags, const char *arch, const char *tune,
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{ "-mcrc32", OPTION_MASK_ISA_CRC32 },
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{ "-maes", OPTION_MASK_ISA_AES },
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{ "-mpclmul", OPTION_MASK_ISA_PCLMUL },
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{ "-mfsgsbase", OPTION_MASK_ISA_FSGSBASE },
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{ "-mrdrnd", OPTION_MASK_ISA_RDRND },
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{ "-mf16c", OPTION_MASK_ISA_F16C },
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};
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/* Flag options. */
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@ -2779,7 +2830,10 @@ override_options (bool main_args_p)
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PTA_MOVBE = 1 << 20,
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PTA_FMA4 = 1 << 21,
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PTA_XOP = 1 << 22,
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PTA_LWP = 1 << 23
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PTA_LWP = 1 << 23,
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PTA_FSGSBASE = 1 << 24,
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PTA_RDRND = 1 << 25,
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PTA_F16C = 1 << 26
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};
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static struct pta
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@ -3155,6 +3209,15 @@ override_options (bool main_args_p)
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if (processor_alias_table[i].flags & PTA_PCLMUL
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&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
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ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
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if (processor_alias_table[i].flags & PTA_FSGSBASE
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&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FSGSBASE))
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ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE;
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if (processor_alias_table[i].flags & PTA_RDRND
|
||||
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_RDRND))
|
||||
ix86_isa_flags |= OPTION_MASK_ISA_RDRND;
|
||||
if (processor_alias_table[i].flags & PTA_F16C
|
||||
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_F16C))
|
||||
ix86_isa_flags |= OPTION_MASK_ISA_F16C;
|
||||
if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
|
||||
x86_prefetch_sse = true;
|
||||
|
||||
@ -3829,6 +3892,9 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
|
||||
IX86_ATTR_ISA ("fma4", OPT_mfma4),
|
||||
IX86_ATTR_ISA ("xop", OPT_mxop),
|
||||
IX86_ATTR_ISA ("lwp", OPT_mlwp),
|
||||
IX86_ATTR_ISA ("fsgsbase", OPT_mfsgsbase),
|
||||
IX86_ATTR_ISA ("rdrnd", OPT_mrdrnd),
|
||||
IX86_ATTR_ISA ("f16c", OPT_mf16c),
|
||||
|
||||
/* string options */
|
||||
IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
|
||||
@ -21628,6 +21694,27 @@ enum ix86_builtins
|
||||
|
||||
IX86_BUILTIN_CLZS,
|
||||
|
||||
/* FSGSBASE instructions. */
|
||||
IX86_BUILTIN_RDFSBASE32,
|
||||
IX86_BUILTIN_RDFSBASE64,
|
||||
IX86_BUILTIN_RDGSBASE32,
|
||||
IX86_BUILTIN_RDGSBASE64,
|
||||
IX86_BUILTIN_WRFSBASE32,
|
||||
IX86_BUILTIN_WRFSBASE64,
|
||||
IX86_BUILTIN_WRGSBASE32,
|
||||
IX86_BUILTIN_WRGSBASE64,
|
||||
|
||||
/* RDRND instructions. */
|
||||
IX86_BUILTIN_RDRAND16,
|
||||
IX86_BUILTIN_RDRAND32,
|
||||
IX86_BUILTIN_RDRAND64,
|
||||
|
||||
/* F16C instructions. */
|
||||
IX86_BUILTIN_CVTPH2PS,
|
||||
IX86_BUILTIN_CVTPH2PS256,
|
||||
IX86_BUILTIN_CVTPS2PH,
|
||||
IX86_BUILTIN_CVTPS2PH256,
|
||||
|
||||
IX86_BUILTIN_MAX
|
||||
};
|
||||
|
||||
@ -21902,6 +21989,20 @@ static const struct builtin_description bdesc_special_args[] =
|
||||
{ OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
|
||||
{ OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
|
||||
|
||||
/* FSGSBASE */
|
||||
{ OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
|
||||
{ OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
|
||||
{ OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
|
||||
{ OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
|
||||
{ OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
|
||||
{ OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
|
||||
{ OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
|
||||
{ OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
|
||||
|
||||
/* RDRND */
|
||||
{ OPTION_MASK_ISA_RDRND, CODE_FOR_rdrandhi, "__builtin_ia32_rdrand16", IX86_BUILTIN_RDRAND16, UNKNOWN, (int) UINT16_FTYPE_VOID },
|
||||
{ OPTION_MASK_ISA_RDRND, CODE_FOR_rdrandsi, "__builtin_ia32_rdrand32", IX86_BUILTIN_RDRAND32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
|
||||
{ OPTION_MASK_ISA_RDRND | OPTION_MASK_ISA_64BIT, CODE_FOR_rdranddi, "__builtin_ia32_rdrand64", IX86_BUILTIN_RDRAND64, UNKNOWN, (int) UINT64_FTYPE_VOID },
|
||||
};
|
||||
|
||||
/* Builtins with variable number of arguments. */
|
||||
@ -22528,6 +22629,12 @@ static const struct builtin_description bdesc_args[] =
|
||||
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
|
||||
|
||||
{ OPTION_MASK_ISA_ABM, CODE_FOR_clzhi2_abm, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
|
||||
|
||||
/* F16C */
|
||||
{ OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
|
||||
{ OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
|
||||
{ OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
|
||||
{ OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
|
||||
};
|
||||
|
||||
/* FMA4 and XOP. */
|
||||
@ -23768,6 +23875,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
|
||||
case V8SF_FTYPE_V8SF:
|
||||
case V8SF_FTYPE_V8SI:
|
||||
case V8SF_FTYPE_V4SF:
|
||||
case V8SF_FTYPE_V8HI:
|
||||
case V4SI_FTYPE_V4SI:
|
||||
case V4SI_FTYPE_V16QI:
|
||||
case V4SI_FTYPE_V4SF:
|
||||
@ -23784,6 +23892,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
|
||||
case V4SF_FTYPE_V4SI:
|
||||
case V4SF_FTYPE_V8SF:
|
||||
case V4SF_FTYPE_V4DF:
|
||||
case V4SF_FTYPE_V8HI:
|
||||
case V4SF_FTYPE_V2DF:
|
||||
case V2DI_FTYPE_V2DI:
|
||||
case V2DI_FTYPE_V16QI:
|
||||
@ -23886,6 +23995,8 @@ ix86_expand_args_builtin (const struct builtin_description *d,
|
||||
nargs_constant = 1;
|
||||
break;
|
||||
case V8HI_FTYPE_V8HI_INT:
|
||||
case V8HI_FTYPE_V8SF_INT:
|
||||
case V8HI_FTYPE_V4SF_INT:
|
||||
case V8SF_FTYPE_V8SF_INT:
|
||||
case V4SI_FTYPE_V4SI_INT:
|
||||
case V4SI_FTYPE_V8SI_INT:
|
||||
@ -24133,7 +24244,16 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
|
||||
case VOID_FTYPE_VOID:
|
||||
emit_insn (GEN_FCN (icode) (target));
|
||||
return 0;
|
||||
case VOID_FTYPE_UINT64:
|
||||
case VOID_FTYPE_UNSIGNED:
|
||||
nargs = 0;
|
||||
klass = store;
|
||||
memory = 0;
|
||||
break;
|
||||
break;
|
||||
case UINT64_FTYPE_VOID:
|
||||
case UNSIGNED_FTYPE_VOID:
|
||||
case UINT16_FTYPE_VOID:
|
||||
nargs = 0;
|
||||
klass = load;
|
||||
memory = 0;
|
||||
@ -24212,7 +24332,10 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
|
||||
arg = CALL_EXPR_ARG (exp, 0);
|
||||
op = expand_normal (arg);
|
||||
gcc_assert (target == 0);
|
||||
target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
|
||||
if (memory)
|
||||
target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
|
||||
else
|
||||
target = force_reg (tmode, op);
|
||||
arg_adjust = 1;
|
||||
}
|
||||
else
|
||||
|
||||
@ -66,6 +66,9 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
#define TARGET_AES OPTION_ISA_AES
|
||||
#define TARGET_PCLMUL OPTION_ISA_PCLMUL
|
||||
#define TARGET_CMPXCHG16B OPTION_ISA_CX16
|
||||
#define TARGET_FSGSBASE OPTION_ISA_FSGSBASE
|
||||
#define TARGET_RDRND OPTION_ISA_RDRND
|
||||
#define TARGET_F16C OPTION_ISA_F16C
|
||||
|
||||
|
||||
/* SSE4.1 defines round instructions */
|
||||
|
||||
@ -226,6 +226,8 @@
|
||||
UNSPEC_MASKSTORE
|
||||
UNSPEC_CAST
|
||||
UNSPEC_VTESTP
|
||||
UNSPEC_VCVTPH2PS
|
||||
UNSPEC_VCVTPS2PH
|
||||
])
|
||||
|
||||
(define_c_enum "unspecv" [
|
||||
@ -254,6 +256,11 @@
|
||||
UNSPECV_SLWP_INTRINSIC
|
||||
UNSPECV_LWPVAL_INTRINSIC
|
||||
UNSPECV_LWPINS_INTRINSIC
|
||||
UNSPECV_RDFSBASE
|
||||
UNSPECV_RDGSBASE
|
||||
UNSPECV_WRFSBASE
|
||||
UNSPECV_WRGSBASE
|
||||
UNSPECV_RDRAND
|
||||
])
|
||||
|
||||
;; Constants to represent pcomtrue/pcomfalse variants
|
||||
@ -18477,6 +18484,46 @@
|
||||
(set (attr "length")
|
||||
(symbol_ref "ix86_attr_length_address_default (insn) + 9"))])
|
||||
|
||||
(define_insn "rdfsbase<mode>"
|
||||
[(set (match_operand:SWI48 0 "register_operand" "=r")
|
||||
(unspec_volatile:SWI48 [(const_int 0)] UNSPECV_RDFSBASE))]
|
||||
"TARGET_64BIT && TARGET_FSGSBASE"
|
||||
"rdfsbase %0"
|
||||
[(set_attr "type" "other")
|
||||
(set_attr "prefix_extra" "2")])
|
||||
|
||||
(define_insn "rdgsbase<mode>"
|
||||
[(set (match_operand:SWI48 0 "register_operand" "=r")
|
||||
(unspec_volatile:SWI48 [(const_int 0)] UNSPECV_RDGSBASE))]
|
||||
"TARGET_64BIT && TARGET_FSGSBASE"
|
||||
"rdgsbase %0"
|
||||
[(set_attr "type" "other")
|
||||
(set_attr "prefix_extra" "2")])
|
||||
|
||||
(define_insn "wrfsbase<mode>"
|
||||
[(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")]
|
||||
UNSPECV_WRFSBASE)]
|
||||
"TARGET_64BIT && TARGET_FSGSBASE"
|
||||
"wrfsbase %0"
|
||||
[(set_attr "type" "other")
|
||||
(set_attr "prefix_extra" "2")])
|
||||
|
||||
(define_insn "wrgsbase<mode>"
|
||||
[(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")]
|
||||
UNSPECV_WRGSBASE)]
|
||||
"TARGET_64BIT && TARGET_FSGSBASE"
|
||||
"wrgsbase %0"
|
||||
[(set_attr "type" "other")
|
||||
(set_attr "prefix_extra" "2")])
|
||||
|
||||
(define_insn "rdrand<mode>"
|
||||
[(set (match_operand:SWI248 0 "register_operand" "=r")
|
||||
(unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDRAND))]
|
||||
"TARGET_RDRND"
|
||||
"rdrand %0"
|
||||
[(set_attr "type" "other")
|
||||
(set_attr "prefix_extra" "1")])
|
||||
|
||||
(include "mmx.md")
|
||||
(include "sse.md")
|
||||
(include "sync.md")
|
||||
|
||||
@ -363,3 +363,15 @@ Support PCLMUL built-in functions and code generation
|
||||
msse2avx
|
||||
Target Report Var(ix86_sse2avx)
|
||||
Encode SSE instructions with VEX prefix
|
||||
|
||||
mfsgsbase
|
||||
Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) VarExists Save
|
||||
Support FSGSBASE built-in functions and code generation
|
||||
|
||||
mrdrnd
|
||||
Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) VarExists Save
|
||||
Support RDRND built-in functions and code generation
|
||||
|
||||
mf16c
|
||||
Target Report Mask(ISA_F16C) Var(ix86_isa_flags) VarExists Save
|
||||
Support F16C built-in functions and code generation
|
||||
|
||||
@ -56,4 +56,148 @@
|
||||
#include <avxintrin.h>
|
||||
#endif
|
||||
|
||||
#ifdef __RDRND__
|
||||
extern __inline unsigned short
|
||||
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_rdrand_u16 (void)
|
||||
{
|
||||
return __builtin_ia32_rdrand16 ();
|
||||
}
|
||||
|
||||
extern __inline unsigned int
|
||||
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_rdrand_u32 (void)
|
||||
{
|
||||
return __builtin_ia32_rdrand32 ();
|
||||
}
|
||||
#endif /* __RDRND__ */
|
||||
|
||||
#ifdef __x86_64__
|
||||
#ifdef __FSGSBASE__
|
||||
extern __inline unsigned int
|
||||
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_readfsbase_u32 (void)
|
||||
{
|
||||
return __builtin_ia32_rdfsbase32 ();
|
||||
}
|
||||
|
||||
extern __inline unsigned long long
|
||||
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_readfsbase_u64 (void)
|
||||
{
|
||||
return __builtin_ia32_rdfsbase64 ();
|
||||
}
|
||||
|
||||
extern __inline unsigned int
|
||||
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_readgsbase_u32 (void)
|
||||
{
|
||||
return __builtin_ia32_rdgsbase32 ();
|
||||
}
|
||||
|
||||
extern __inline unsigned long long
|
||||
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_readgsbase_u64 (void)
|
||||
{
|
||||
return __builtin_ia32_rdgsbase64 ();
|
||||
}
|
||||
|
||||
extern __inline void
|
||||
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_writefsbase_u32 (unsigned int __B)
|
||||
{
|
||||
__builtin_ia32_wrfsbase32 (__B);
|
||||
}
|
||||
|
||||
extern __inline void
|
||||
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_writefsbase_u64 (unsigned long long __B)
|
||||
{
|
||||
__builtin_ia32_wrfsbase64 (__B);
|
||||
}
|
||||
|
||||
extern __inline void
|
||||
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_writegsbase_u32 (unsigned int __B)
|
||||
{
|
||||
__builtin_ia32_wrgsbase32 (__B);
|
||||
}
|
||||
|
||||
extern __inline void
|
||||
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_writegsbase_u64 (unsigned long long __B)
|
||||
{
|
||||
__builtin_ia32_wrgsbase64 (__B);
|
||||
}
|
||||
#endif /* __FSGSBASE__ */
|
||||
|
||||
#ifdef __RDRND__
|
||||
extern __inline unsigned long long
|
||||
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_rdrand_u64 (void)
|
||||
{
|
||||
return __builtin_ia32_rdrand64 ();
|
||||
}
|
||||
#endif /* __RDRND__ */
|
||||
#endif /* __x86_64__ */
|
||||
|
||||
#ifdef __F16C__
|
||||
extern __inline float __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_cvtsh_ss (unsigned short __S)
|
||||
{
|
||||
__v8hi __H = __extension__ (__v8hi){ __S, 0, 0, 0, 0, 0, 0, 0 };
|
||||
__v4sf __A = __builtin_ia32_vcvtph2ps (__H);
|
||||
return __builtin_ia32_vec_ext_v4sf (__A, 0);
|
||||
}
|
||||
|
||||
extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_mm_cvtph_ps (__m128i __A)
|
||||
{
|
||||
return (__m128) __builtin_ia32_vcvtph2ps ((__v8hi) __A);
|
||||
}
|
||||
|
||||
extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_mm256_cvtph_ps (__m128i __A)
|
||||
{
|
||||
return (__m256) __builtin_ia32_vcvtph2ps256 ((__v8hi) __A);
|
||||
}
|
||||
|
||||
#ifdef __OPTIMIZE__
|
||||
extern __inline unsigned short __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_cvtss_sh (float __F, const int __I)
|
||||
{
|
||||
__v4sf __A = __extension__ (__v4sf){ __F, 0, 0, 0 };
|
||||
__v8hi __H = __builtin_ia32_vcvtps2ph (__A, __I);
|
||||
return (unsigned short) __builtin_ia32_vec_ext_v8hi (__H, 0);
|
||||
}
|
||||
|
||||
extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_mm_cvtps_ph (__m128 __A, const int __I)
|
||||
{
|
||||
return (__m128i) __builtin_ia32_vcvtps2ph ((__v4sf) __A, __I);
|
||||
}
|
||||
|
||||
extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_mm256_cvtps_ph (__m256 __A, const int __I)
|
||||
{
|
||||
return (__m128i) __builtin_ia32_vcvtps2ph256 ((__v8sf) __A, __I);
|
||||
}
|
||||
#else
|
||||
#define _cvtss_sh(__F, __I) \
|
||||
(__extension__ \
|
||||
({ \
|
||||
__v4sf __A = __extension__ (__v4sf){ __F, 0, 0, 0 }; \
|
||||
__v8hi __H = __builtin_ia32_vcvtps2ph (__A, __I); \
|
||||
(unsigned short) __builtin_ia32_vec_ext_v8hi (__H, 0); \
|
||||
}))
|
||||
|
||||
#define _mm_cvtps_ph(A, I) \
|
||||
((__m128i) __builtin_ia32_vcvtps2ph ((__v4sf)(__m128) A, (int) (I)))
|
||||
|
||||
#define _mm256_cvtps_ph(A, I) \
|
||||
((__m128i) __builtin_ia32_vcvtps2ph256 ((__v8sf)(__m256) A, (int) (I)))
|
||||
#endif
|
||||
|
||||
#endif /* __F16C__ */
|
||||
|
||||
#endif /* _IMMINTRIN_H_INCLUDED */
|
||||
|
||||
@ -12322,3 +12322,81 @@
|
||||
(set_attr "length_immediate" "1,*")
|
||||
(set_attr "prefix" "vex")
|
||||
(set_attr "mode" "<avxvecmode>")])
|
||||
|
||||
(define_insn "vcvtph2ps"
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=x")
|
||||
(vec_select:V4SF
|
||||
(unspec:V8SF [(match_operand:V8HI 1 "register_operand" "x")]
|
||||
UNSPEC_VCVTPH2PS)
|
||||
(parallel [(const_int 0) (const_int 1)
|
||||
(const_int 1) (const_int 2)])))]
|
||||
"TARGET_F16C"
|
||||
"vcvtph2ps\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
(set_attr "prefix" "vex")
|
||||
(set_attr "mode" "V4SF")])
|
||||
|
||||
(define_insn "*vcvtph2ps_load"
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=x")
|
||||
(unspec:V4SF [(match_operand:V4HI 1 "memory_operand" "m")]
|
||||
UNSPEC_VCVTPH2PS))]
|
||||
"TARGET_F16C"
|
||||
"vcvtph2ps\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
(set_attr "prefix" "vex")
|
||||
(set_attr "mode" "V8SF")])
|
||||
|
||||
(define_insn "vcvtph2ps256"
|
||||
[(set (match_operand:V8SF 0 "register_operand" "=x")
|
||||
(unspec:V8SF [(match_operand:V8HI 1 "nonimmediate_operand" "xm")]
|
||||
UNSPEC_VCVTPH2PS))]
|
||||
"TARGET_F16C"
|
||||
"vcvtph2ps\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
(set_attr "prefix" "vex")
|
||||
(set_attr "mode" "V8SF")])
|
||||
|
||||
(define_expand "vcvtps2ph"
|
||||
[(set (match_operand:V8HI 0 "register_operand" "")
|
||||
(vec_concat:V8HI
|
||||
(unspec:V4HI [(match_operand:V4SF 1 "register_operand" "")
|
||||
(match_operand:SI 2 "immediate_operand" "")]
|
||||
UNSPEC_VCVTPS2PH)
|
||||
(match_dup 3)))]
|
||||
"TARGET_F16C"
|
||||
"operands[3] = CONST0_RTX (V4HImode);")
|
||||
|
||||
(define_insn "*vcvtps2ph"
|
||||
[(set (match_operand:V8HI 0 "register_operand" "=x")
|
||||
(vec_concat:V8HI
|
||||
(unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x")
|
||||
(match_operand:SI 2 "immediate_operand" "N")]
|
||||
UNSPEC_VCVTPS2PH)
|
||||
(match_operand:V4HI 3 "const0_operand" "")))]
|
||||
"TARGET_F16C"
|
||||
"vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
(set_attr "prefix" "vex")
|
||||
(set_attr "mode" "V4SF")])
|
||||
|
||||
(define_insn "*vcvtps2ph_store"
|
||||
[(set (match_operand:V4HI 0 "memory_operand" "=m")
|
||||
(unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x")
|
||||
(match_operand:SI 2 "immediate_operand" "N")]
|
||||
UNSPEC_VCVTPS2PH))]
|
||||
"TARGET_F16C"
|
||||
"vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
(set_attr "prefix" "vex")
|
||||
(set_attr "mode" "V4SF")])
|
||||
|
||||
(define_insn "vcvtps2ph256"
|
||||
[(set (match_operand:V8HI 0 "nonimmediate_operand" "=xm")
|
||||
(unspec:V8HI [(match_operand:V8SF 1 "register_operand" "x")
|
||||
(match_operand:SI 2 "immediate_operand" "N")]
|
||||
UNSPEC_VCVTPS2PH))]
|
||||
"TARGET_F16C"
|
||||
"vcvtps2ph\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
(set_attr "prefix" "vex")
|
||||
(set_attr "mode" "V8SF")])
|
||||
|
||||
@ -8958,6 +8958,31 @@ used.
|
||||
Generates the @code{pclmulqdq} machine instruction.
|
||||
@end table
|
||||
|
||||
The following built-in function is available when @option{-mfsgsbase} is
|
||||
used. All of them generate the machine instruction that is part of the
|
||||
name.
|
||||
|
||||
@smallexample
|
||||
unsigned int __builtin_ia32_rdfsbase32 (void)
|
||||
unsigned long long __builtin_ia32_rdfsbase64 (void)
|
||||
unsigned int __builtin_ia32_rdgsbase32 (void)
|
||||
unsigned long long __builtin_ia32_rdgsbase64 (void)
|
||||
void _writefsbase_u32 (unsigned int)
|
||||
void _writefsbase_u64 (unsigned long long)
|
||||
void _writegsbase_u32 (unsigned int)
|
||||
void _writegsbase_u64 (unsigned long long)
|
||||
@end smallexample
|
||||
|
||||
The following built-in function is available when @option{-mrdrnd} is
|
||||
used. All of them generate the machine instruction that is part of the
|
||||
name.
|
||||
|
||||
@smallexample
|
||||
unsigned short __builtin_ia32_rdrand16 (void)
|
||||
unsigned int __builtin_ia32_rdrand32 (void)
|
||||
unsigned long long __builtin_ia32_rdrand64 (void)
|
||||
@end smallexample
|
||||
|
||||
The following built-in functions are available when @option{-msse4a} is used.
|
||||
All of them generate the machine instruction that is part of the name.
|
||||
|
||||
|
||||
@ -591,7 +591,7 @@ Objective-C and Objective-C++ Dialects}.
|
||||
-mincoming-stack-boundary=@var{num}
|
||||
-mcld -mcx16 -msahf -mmovbe -mcrc32 -mrecip @gol
|
||||
-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
|
||||
-maes -mpclmul -mfused-madd @gol
|
||||
-maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfused-madd @gol
|
||||
-msse4a -m3dnow -mpopcnt -mabm -mfma4 -mxop -mlwp @gol
|
||||
-mthreads -mno-align-stringops -minline-all-stringops @gol
|
||||
-minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol
|
||||
@ -12226,6 +12226,12 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
|
||||
@itemx -mno-aes
|
||||
@itemx -mpclmul
|
||||
@itemx -mno-pclmul
|
||||
@itemx -mfsgsbase
|
||||
@itemx -mno-fsgsbase
|
||||
@itemx -mrdrnd
|
||||
@itemx -mno-rdrnd
|
||||
@itemx -mf16c
|
||||
@itemx -mno-f16c
|
||||
@itemx -msse4a
|
||||
@itemx -mno-sse4a
|
||||
@itemx -mfma4
|
||||
@ -12247,8 +12253,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
|
||||
@opindex m3dnow
|
||||
@opindex mno-3dnow
|
||||
These switches enable or disable the use of instructions in the MMX,
|
||||
SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, SSE4A, FMA4, XOP,
|
||||
LWP, ABM or 3DNow!@: extended instruction sets.
|
||||
SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, FSGSBASE, RDRND,
|
||||
F16C, SSE4A, FMA4, XOP, LWP, ABM or 3DNow!@: extended instruction sets.
|
||||
These extensions are also available as built-in functions: see
|
||||
@ref{X86 Built-in Functions}, for details of the functions enabled and
|
||||
disabled by these switches.
|
||||
|
||||
@ -1,3 +1,45 @@
|
||||
2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
AVX Programming Reference (June, 2010)
|
||||
* g++.dg/other/i386-2.C: Add -mfsgsbase -mrdrnd -mf16c.
|
||||
* g++.dg/other/i386-3.C: Likewise.
|
||||
* gcc.target/i386/sse-12.c: Likewise.
|
||||
|
||||
* gcc.target/i386/f16c-check.h: New.
|
||||
* gcc.target/i386/rdfsbase-1.c: Likewise.
|
||||
* gcc.target/i386/rdfsbase-2.c: Likewise.
|
||||
* gcc.target/i386/rdgsbase-1.c: Likewise.
|
||||
* gcc.target/i386/rdgsbase-2.c: Likewise.
|
||||
* gcc.target/i386/rdrand-1.c: Likewise.
|
||||
* gcc.target/i386/rdrand-2.c: Likewise.
|
||||
* gcc.target/i386/rdrand-3.c: Likewise.
|
||||
* gcc.target/i386/vcvtph2ps-1.c: Likewise.
|
||||
* gcc.target/i386/vcvtph2ps-2.c: Likewise.
|
||||
* gcc.target/i386/vcvtph2ps-3.c: Likewise.
|
||||
* gcc.target/i386/vcvtps2ph-1.c: Likewise.
|
||||
* gcc.target/i386/vcvtps2ph-2.c: Likewise.
|
||||
* gcc.target/i386/vcvtps2ph-3.c: Likewise.
|
||||
* gcc.target/i386/wrfsbase-1.c: Likewise.
|
||||
* gcc.target/i386/wrfsbase-2.c: Likewise.
|
||||
* gcc.target/i386/wrgsbase-1.c: Likewise.
|
||||
* gcc.target/i386/wrgsbase-2.c: Likewise.
|
||||
|
||||
* gcc.target/i386/sse-13.c: Add -mfsgsbase -mrdrnd -mf16c.
|
||||
(__builtin_ia32_vcvtps2ph): New.
|
||||
(__builtin_ia32_vcvtps2ph256): Likewise.
|
||||
|
||||
* gcc.target/i386/sse-14.c: Add -mfsgsbase -mrdrnd -mf16c.
|
||||
Test _cvtss_sh, _mm_cvtps_ph and _mm256_cvtps_ph.
|
||||
|
||||
* gcc.target/i386/sse-22.c: Add fsgsbase,rdrnd,f16c.
|
||||
Test _cvtss_sh, _mm_cvtps_ph and _mm256_cvtps_ph.
|
||||
|
||||
* gcc.target/i386/sse-23.c (__builtin_ia32_vcvtps2ph): New.
|
||||
(__builtin_ia32_vcvtps2ph256): Likewise.
|
||||
Add fsgsbase,rdrnd,f16c.
|
||||
|
||||
* lib/target-supports.exp (check_effective_target_f16c): New.
|
||||
|
||||
2010-07-05 Jakub Jelinek <jakub@redhat.com>
|
||||
|
||||
* gcc.dg/guality/nrv-1.c: New test.
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
|
||||
/* { dg-options "-O -pedantic-errors -march=k8 -m3dnow -mavx -mxop -maes -mpclmul -mpopcnt -mabm -mlwp" } */
|
||||
/* { dg-options "-O -pedantic-errors -march=k8 -m3dnow -mavx -mxop -maes -mpclmul -mpopcnt -mabm -mlwp -mfsgsbase -mrdrnd -mf16c" } */
|
||||
|
||||
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, xopintrin.h, abmintrin.h,
|
||||
lwpintrin.h, popcntintrin.h and mm3dnow.h are usable with
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
|
||||
/* { dg-options "-O -fkeep-inline-functions -march=k8 -m3dnow -mavx -mxop -maes -mpclmul -mpopcnt -mabm -mlwp" } */
|
||||
/* { dg-options "-O -fkeep-inline-functions -march=k8 -m3dnow -mavx -mxop -maes -mpclmul -mpopcnt -mabm -mlwp -mfsgsbase -mrdrnd -mf16c" } */
|
||||
|
||||
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, xopintrin.h, abmintrin.h,
|
||||
lwpintrin.h, popcntintrin.h and mm3dnow.h are usable with
|
||||
|
||||
30
gcc/testsuite/gcc.target/i386/f16c-check.h
Normal file
30
gcc/testsuite/gcc.target/i386/f16c-check.h
Normal file
@ -0,0 +1,30 @@
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include "cpuid.h"
|
||||
#include "m256-check.h"
|
||||
|
||||
static void f16c_test (void);
|
||||
|
||||
int
|
||||
main ()
|
||||
{
|
||||
unsigned int eax, ebx, ecx, edx;
|
||||
|
||||
if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
|
||||
return 0;
|
||||
|
||||
/* Run F16C test only if host has F16C support. */
|
||||
if (ecx & bit_F16C)
|
||||
{
|
||||
f16c_test ();
|
||||
#ifdef DEBUG
|
||||
printf ("PASSED\n");
|
||||
#endif
|
||||
}
|
||||
#ifdef DEBUG
|
||||
else
|
||||
printf ("SKIPPED\n");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
12
gcc/testsuite/gcc.target/i386/rdfsbase-1.c
Normal file
12
gcc/testsuite/gcc.target/i386/rdfsbase-1.c
Normal file
@ -0,0 +1,12 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target lp64 } */
|
||||
/* { dg-options "-O2 -mfsgsbase" } */
|
||||
/* { dg-final { scan-assembler "rdfsbase\[ \t]+(%|)eax" } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
unsigned int
|
||||
read_fs_base32 (void)
|
||||
{
|
||||
return _readfsbase_u32 ();
|
||||
}
|
||||
12
gcc/testsuite/gcc.target/i386/rdfsbase-2.c
Normal file
12
gcc/testsuite/gcc.target/i386/rdfsbase-2.c
Normal file
@ -0,0 +1,12 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target lp64 } */
|
||||
/* { dg-options "-O2 -mfsgsbase" } */
|
||||
/* { dg-final { scan-assembler "rdfsbase\[ \t]+(%|)rax" } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
unsigned long long
|
||||
read_fs_base64 (void)
|
||||
{
|
||||
return _readfsbase_u64 ();
|
||||
}
|
||||
12
gcc/testsuite/gcc.target/i386/rdgsbase-1.c
Normal file
12
gcc/testsuite/gcc.target/i386/rdgsbase-1.c
Normal file
@ -0,0 +1,12 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target lp64 } */
|
||||
/* { dg-options "-O2 -mfsgsbase" } */
|
||||
/* { dg-final { scan-assembler "rdgsbase\[ \t]+(%|)eax" } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
unsigned int
|
||||
read_gs_base32 (void)
|
||||
{
|
||||
return _readgsbase_u32 ();
|
||||
}
|
||||
12
gcc/testsuite/gcc.target/i386/rdgsbase-2.c
Normal file
12
gcc/testsuite/gcc.target/i386/rdgsbase-2.c
Normal file
@ -0,0 +1,12 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target lp64 } */
|
||||
/* { dg-options "-O2 -mfsgsbase" } */
|
||||
/* { dg-final { scan-assembler "rdgsbase\[ \t]+(%|)rax" } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
unsigned long long
|
||||
read_gs_base64 (void)
|
||||
{
|
||||
return _readgsbase_u64 ();
|
||||
}
|
||||
11
gcc/testsuite/gcc.target/i386/rdrand-1.c
Normal file
11
gcc/testsuite/gcc.target/i386/rdrand-1.c
Normal file
@ -0,0 +1,11 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mrdrnd " } */
|
||||
/* { dg-final { scan-assembler "rdrand\[ \t]+(%|)ax" } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
unsigned short
|
||||
read_rdrand16 (void)
|
||||
{
|
||||
return _rdrand_u16 ();
|
||||
}
|
||||
11
gcc/testsuite/gcc.target/i386/rdrand-2.c
Normal file
11
gcc/testsuite/gcc.target/i386/rdrand-2.c
Normal file
@ -0,0 +1,11 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mrdrnd " } */
|
||||
/* { dg-final { scan-assembler "rdrand\[ \t]+(%|)eax" } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
unsigned int
|
||||
read_rdrand32 (void)
|
||||
{
|
||||
return _rdrand_u32 ();
|
||||
}
|
||||
12
gcc/testsuite/gcc.target/i386/rdrand-3.c
Normal file
12
gcc/testsuite/gcc.target/i386/rdrand-3.c
Normal file
@ -0,0 +1,12 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target lp64 } */
|
||||
/* { dg-options "-O2 -mrdrnd " } */
|
||||
/* { dg-final { scan-assembler "rdrand\[ \t]+(%|)rax" } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
unsigned long long
|
||||
read_rdrand64 (void)
|
||||
{
|
||||
return _rdrand_u64 ();
|
||||
}
|
||||
@ -2,7 +2,7 @@
|
||||
abmintrin.h, lwpintrin.h, popcntintrin.h and mm_malloc.h are usable
|
||||
with -O -std=c89 -pedantic-errors. */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -m3dnow -mavx -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlwp" } */
|
||||
/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -m3dnow -mavx -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlwp -mfsgsbase -mrdrnd -mf16c" } */
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -maes -mpclmul -mpopcnt -mabm -mlwp" } */
|
||||
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -maes -mpclmul -mpopcnt -mabm -mlwp -mfsgsbase -mrdrnd -mf16c" } */
|
||||
|
||||
#include <mm_malloc.h>
|
||||
|
||||
@ -50,6 +50,8 @@
|
||||
#define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1)
|
||||
#define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1)
|
||||
#define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1)
|
||||
#define __builtin_ia32_vcvtps2ph(A, I) __builtin_ia32_vcvtps2ph(A, 1)
|
||||
#define __builtin_ia32_vcvtps2ph256(A, I) __builtin_ia32_vcvtps2ph256(A, 1)
|
||||
|
||||
/* wmmintrin.h */
|
||||
#define __builtin_ia32_aeskeygenassist128(X, C) __builtin_ia32_aeskeygenassist128(X, 1)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -msse4a -maes -mpclmul -mpopcnt -mabm -mlwp" } */
|
||||
/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -msse4a -maes -mpclmul -mpopcnt -mabm -mlwp -mfsgsbase -mrdrnd -mf16c" } */
|
||||
|
||||
#include <mm_malloc.h>
|
||||
|
||||
@ -89,6 +89,9 @@ test_2 (_mm256_insert_epi64, __m256i, __m256i, long long, 1)
|
||||
#endif
|
||||
test_1 (_mm256_round_pd, __m256d, __m256d, 1)
|
||||
test_1 (_mm256_round_ps, __m256, __m256, 1)
|
||||
test_1 (_cvtss_sh, unsigned short, float, 1)
|
||||
test_1 (_mm_cvtps_ph, __m128i, __m128, 1)
|
||||
test_1 (_mm256_cvtps_ph, __m128i, __m256, 1)
|
||||
|
||||
/* wmmintrin.h */
|
||||
test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1)
|
||||
|
||||
@ -39,7 +39,7 @@
|
||||
|
||||
|
||||
#ifndef DIFFERENT_PRAGMAS
|
||||
#pragma GCC target ("mmx,3dnow,sse,sse2,sse3,ssse3,sse4.1,sse4.2,sse4a,aes,pclmul,xop,popcnt,abm,lwp")
|
||||
#pragma GCC target ("mmx,3dnow,sse,sse2,sse3,ssse3,sse4.1,sse4.2,sse4a,aes,pclmul,xop,popcnt,abm,lwp,fsgsbase,rdrnd,f16c")
|
||||
#endif
|
||||
|
||||
/* Following intrinsics require immediate arguments. They
|
||||
@ -179,3 +179,12 @@ test_2 ( __lwpins32, unsigned char, unsigned int, unsigned int, 1)
|
||||
test_2 ( __lwpval64, void, unsigned long long, unsigned int, 1)
|
||||
test_2 ( __lwpins64, unsigned char, unsigned long long, unsigned int, 1)
|
||||
#endif
|
||||
|
||||
/* immintrin.h (F16C). */
|
||||
#ifdef DIFFERENT_PRAGMAS
|
||||
#pragma GCC target ("f16c")
|
||||
#endif
|
||||
#include <x86intrin.h>
|
||||
test_1 (_cvtss_sh, unsigned short, float, 1)
|
||||
test_1 (_mm_cvtps_ph, __m128i, __m128, 1)
|
||||
test_1 (_mm256_cvtps_ph, __m128i, __m256, 1)
|
||||
|
||||
@ -126,6 +126,8 @@
|
||||
#define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1)
|
||||
#define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1)
|
||||
#define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1)
|
||||
#define __builtin_ia32_vcvtps2ph(A, I) __builtin_ia32_vcvtps2ph(A, 1)
|
||||
#define __builtin_ia32_vcvtps2ph256(A, I) __builtin_ia32_vcvtps2ph256(A, 1)
|
||||
|
||||
/* xopintrin.h */
|
||||
#define __builtin_ia32_vprotbi(A, B) __builtin_ia32_vprotbi(A,1)
|
||||
@ -139,7 +141,7 @@
|
||||
#define __builtin_ia32_lwpins32(D2, D1, F) __builtin_ia32_lwpins32 (D2, D1, 1)
|
||||
#define __builtin_ia32_lwpins64(D2, D1, F) __builtin_ia32_lwpins64 (D2, D1, 1)
|
||||
|
||||
#pragma GCC target ("3dnow,sse4,sse4a,aes,pclmul,xop,abm,popcnt,lwp")
|
||||
#pragma GCC target ("3dnow,sse4,sse4a,aes,pclmul,xop,abm,popcnt,lwp,fsgsbase,rdrnd,f16c")
|
||||
#include <wmmintrin.h>
|
||||
#include <smmintrin.h>
|
||||
#include <mm3dnow.h>
|
||||
|
||||
28
gcc/testsuite/gcc.target/i386/vcvtph2ps-1.c
Normal file
28
gcc/testsuite/gcc.target/i386/vcvtph2ps-1.c
Normal file
@ -0,0 +1,28 @@
|
||||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target f16c } */
|
||||
/* { dg-options "-O2 -mf16c" } */
|
||||
|
||||
#include "f16c-check.h"
|
||||
|
||||
static void
|
||||
f16c_test (void)
|
||||
{
|
||||
union128i_w val;
|
||||
union128 res;
|
||||
float exp[4];
|
||||
|
||||
exp[0] = 1;
|
||||
exp[1] = -2;
|
||||
exp[2] = -1;
|
||||
exp[3] = 2;
|
||||
|
||||
val.a[0] = 0x3c00;
|
||||
val.a[1] = 0xc000;
|
||||
val.a[2] = 0xbc00;
|
||||
val.a[3] = 0x4000;
|
||||
|
||||
res.x = _mm_cvtph_ps (val.x);
|
||||
|
||||
if (check_union128 (res, exp))
|
||||
abort ();
|
||||
}
|
||||
36
gcc/testsuite/gcc.target/i386/vcvtph2ps-2.c
Normal file
36
gcc/testsuite/gcc.target/i386/vcvtph2ps-2.c
Normal file
@ -0,0 +1,36 @@
|
||||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target f16c } */
|
||||
/* { dg-options "-O2 -mf16c" } */
|
||||
|
||||
#include "f16c-check.h"
|
||||
|
||||
static void
|
||||
f16c_test (void)
|
||||
{
|
||||
union256 res;
|
||||
union128i_w val;
|
||||
float exp[8];
|
||||
|
||||
exp[0] = 1;
|
||||
exp[1] = 2;
|
||||
exp[2] = 4;
|
||||
exp[3] = 8;
|
||||
exp[4] = -1;
|
||||
exp[5] = -2;
|
||||
exp[6] = -4;
|
||||
exp[7] = -8;
|
||||
|
||||
val.a[0] = 0x3c00;
|
||||
val.a[1] = 0x4000;
|
||||
val.a[2] = 0x4400;
|
||||
val.a[3] = 0x4800;
|
||||
val.a[4] = 0xbc00;
|
||||
val.a[5] = 0xc000;
|
||||
val.a[6] = 0xc400;
|
||||
val.a[7] = 0xc800;
|
||||
|
||||
res.x = _mm256_cvtph_ps (val.x);
|
||||
|
||||
if (check_union256 (res, exp))
|
||||
abort ();
|
||||
}
|
||||
18
gcc/testsuite/gcc.target/i386/vcvtph2ps-3.c
Normal file
18
gcc/testsuite/gcc.target/i386/vcvtph2ps-3.c
Normal file
@ -0,0 +1,18 @@
|
||||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target f16c } */
|
||||
/* { dg-options "-O2 -mf16c" } */
|
||||
|
||||
#include "f16c-check.h"
|
||||
|
||||
static void
|
||||
f16c_test (void)
|
||||
{
|
||||
unsigned short val = 0xc000;
|
||||
float exp = -2;
|
||||
float res;
|
||||
|
||||
res = _cvtsh_ss (val);
|
||||
|
||||
if (res != exp)
|
||||
abort ();
|
||||
}
|
||||
32
gcc/testsuite/gcc.target/i386/vcvtps2ph-1.c
Normal file
32
gcc/testsuite/gcc.target/i386/vcvtps2ph-1.c
Normal file
@ -0,0 +1,32 @@
|
||||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target f16c } */
|
||||
/* { dg-options "-O2 -mf16c" } */
|
||||
|
||||
#include "f16c-check.h"
|
||||
|
||||
static void
|
||||
f16c_test (void)
|
||||
{
|
||||
union128 val;
|
||||
union128i_w res;
|
||||
short exp[8];
|
||||
|
||||
val.a[0] = 1;
|
||||
val.a[1] = -2;
|
||||
val.a[2] = -1;
|
||||
val.a[3] = 2;
|
||||
|
||||
exp[0] = 0x3c00;
|
||||
exp[1] = 0xc000;
|
||||
exp[2] = 0xbc00;
|
||||
exp[3] = 0x4000;
|
||||
exp[4] = 0;
|
||||
exp[5] = 0;
|
||||
exp[6] = 0;
|
||||
exp[7] = 0;
|
||||
|
||||
res.x = _mm_cvtps_ph (val.x, 0);
|
||||
|
||||
if (check_union128i_w (res, exp))
|
||||
abort ();
|
||||
}
|
||||
36
gcc/testsuite/gcc.target/i386/vcvtps2ph-2.c
Normal file
36
gcc/testsuite/gcc.target/i386/vcvtps2ph-2.c
Normal file
@ -0,0 +1,36 @@
|
||||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target f16c } */
|
||||
/* { dg-options "-O2 -mf16c" } */
|
||||
|
||||
#include "f16c-check.h"
|
||||
|
||||
static void
|
||||
f16c_test (void)
|
||||
{
|
||||
union256 val;
|
||||
union128i_w res;
|
||||
short exp[8];
|
||||
|
||||
val.a[0] = 1;
|
||||
val.a[1] = 2;
|
||||
val.a[2] = 4;
|
||||
val.a[3] = 8;
|
||||
val.a[4] = -1;
|
||||
val.a[5] = -2;
|
||||
val.a[6] = -4;
|
||||
val.a[7] = -8;
|
||||
|
||||
exp[0] = 0x3c00;
|
||||
exp[1] = 0x4000;
|
||||
exp[2] = 0x4400;
|
||||
exp[3] = 0x4800;
|
||||
exp[4] = 0xbc00;
|
||||
exp[5] = 0xc000;
|
||||
exp[6] = 0xc400;
|
||||
exp[7] = 0xc800;
|
||||
|
||||
res.x = _mm256_cvtps_ph (val.x, 0);
|
||||
|
||||
if (check_union128i_w (res, exp))
|
||||
abort ();
|
||||
}
|
||||
18
gcc/testsuite/gcc.target/i386/vcvtps2ph-3.c
Normal file
18
gcc/testsuite/gcc.target/i386/vcvtps2ph-3.c
Normal file
@ -0,0 +1,18 @@
|
||||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target f16c } */
|
||||
/* { dg-options "-O2 -mf16c" } */
|
||||
|
||||
#include "f16c-check.h"
|
||||
|
||||
static void
|
||||
f16c_test (void)
|
||||
{
|
||||
float val = -2;
|
||||
unsigned short exp = 0xc000;
|
||||
unsigned short res;
|
||||
|
||||
res = _cvtss_sh (val, 0);
|
||||
|
||||
if (res != exp)
|
||||
abort ();
|
||||
}
|
||||
12
gcc/testsuite/gcc.target/i386/wrfsbase-1.c
Normal file
12
gcc/testsuite/gcc.target/i386/wrfsbase-1.c
Normal file
@ -0,0 +1,12 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target lp64 } */
|
||||
/* { dg-options "-O2 -mfsgsbase" } */
|
||||
/* { dg-final { scan-assembler "wrfsbase\[ \t]+(%|)edi" } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
void
|
||||
write_fs_base32 (unsigned int base)
|
||||
{
|
||||
_writefsbase_u32 (base);
|
||||
}
|
||||
12
gcc/testsuite/gcc.target/i386/wrfsbase-2.c
Normal file
12
gcc/testsuite/gcc.target/i386/wrfsbase-2.c
Normal file
@ -0,0 +1,12 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target lp64 } */
|
||||
/* { dg-options "-O2 -mfsgsbase" } */
|
||||
/* { dg-final { scan-assembler "wrfsbase\[ \t]+(%|)rdi" } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
void
|
||||
write_fs_base64 (unsigned long long base)
|
||||
{
|
||||
_writefsbase_u64 (base);
|
||||
}
|
||||
12
gcc/testsuite/gcc.target/i386/wrgsbase-1.c
Normal file
12
gcc/testsuite/gcc.target/i386/wrgsbase-1.c
Normal file
@ -0,0 +1,12 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target lp64 } */
|
||||
/* { dg-options "-O2 -mfsgsbase" } */
|
||||
/* { dg-final { scan-assembler "wrgsbase\[ \t]+(%|)edi" } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
void
|
||||
write_gs_base32 (unsigned int base)
|
||||
{
|
||||
_writegsbase_u32 (base);
|
||||
}
|
||||
12
gcc/testsuite/gcc.target/i386/wrgsbase-2.c
Normal file
12
gcc/testsuite/gcc.target/i386/wrgsbase-2.c
Normal file
@ -0,0 +1,12 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target lp64 } */
|
||||
/* { dg-options "-O2 -mfsgsbase" } */
|
||||
/* { dg-final { scan-assembler "wrgsbase\[ \t]+(%|)rdi" } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
void
|
||||
write_gs_base64 (unsigned long long base)
|
||||
{
|
||||
_writegsbase_u64 (base);
|
||||
}
|
||||
@ -3273,6 +3273,19 @@ proc check_effective_target_sse2 { } {
|
||||
} "-O2 -msse2" ]
|
||||
}
|
||||
|
||||
# Return 1 if F16C instructions can be compiled.
|
||||
|
||||
proc check_effective_target_f16c { } {
|
||||
return [check_no_compiler_messages f16c object {
|
||||
#include "immintrin.h"
|
||||
float
|
||||
foo (unsigned short val)
|
||||
{
|
||||
return _cvtsh_ss (val);
|
||||
}
|
||||
} "-O2 -mf16c" ]
|
||||
}
|
||||
|
||||
# Return 1 if C wchar_t type is compatible with char16_t.
|
||||
|
||||
proc check_effective_target_wchar_t_char16_t_compatible { } {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user