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v850e3v5.md (fmasf4): Use fmaf.s on E3V5 architectures.

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* config/v850/v850e3v5.md (fmasf4): Use fmaf.s on E3V5
	architectures.
	(fmssf4): Use fmsf.s on E3V5 architectures.
	(fnmasf4): Use fnmaf.s on E3V5 architectures.
	(fnmssf4): Use fnmsf.s on E3V5 architectures.

From-SVN: r197413
This commit is contained in:
Nick Clifton 2013-04-03 14:06:38 +00:00
parent 1b2253d4f8
commit 4d85233e76
1 changed files with 13 additions and 9 deletions

22
gcc/config/v850/v850.md

@ -2508,14 +2508,18 @@
(set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
;; Note: The FPU-2.0 (ie pre e3v5) versions of these routines do not actually
;; need operand 4 to be the same as operand 0. But the FPU-2.0 versions are
;; also deprecated so the loss of flexibility is unimportant.
;;; multiply-add
(define_insn "fmasf4"
[(set (match_operand:SF 0 "register_operand" "=r")
(fma:SF (match_operand:SF 1 "register_operand" "r")
(match_operand:SF 2 "register_operand" "r")
(match_operand:SF 3 "register_operand" "r")))]
(match_operand:SF 3 "register_operand" "0")))]
"TARGET_USE_FPU"
"maddf.s %2,%1,%3,%0"
{ return TARGET_V850E3V5_UP ? "fmaf.s %1, %2, %0" : "maddf.s %2, %1, %3, %0"; }
[(set_attr "length" "4")
(set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
@ -2525,9 +2529,9 @@
[(set (match_operand:SF 0 "register_operand" "=r")
(fma:SF (match_operand:SF 1 "register_operand" "r")
(match_operand:SF 2 "register_operand" "r")
(neg:SF (match_operand:SF 3 "register_operand" "r"))))]
(neg:SF (match_operand:SF 3 "register_operand" "0"))))]
"TARGET_USE_FPU"
"msubf.s %2,%1,%3,%0"
{ return TARGET_V850E3V5_UP ? "fmsf.s %1, %2, %0" : "msubf.s %2, %1, %3, %0"; }
[(set_attr "length" "4")
(set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
@ -2537,21 +2541,21 @@
[(set (match_operand:SF 0 "register_operand" "=r")
(neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r")
(match_operand:SF 2 "register_operand" "r")
(match_operand:SF 3 "register_operand" "r"))))]
(match_operand:SF 3 "register_operand" "0"))))]
"TARGET_USE_FPU"
"nmaddf.s %2,%1,%3,%0"
{ return TARGET_V850E3V5_UP ? "fnmaf.s %1, %2, %0" : "nmaddf.s %2, %1, %3, %0"; }
[(set_attr "length" "4")
(set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])
;; negative-multiply-subtract
(define_insn "fnmssf4"
[(set (match_operand:SF 0 "register_operand" "=r")
[(set (match_operand:SF 0 "register_operand" "=r")
(neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r")
(match_operand:SF 2 "register_operand" "r")
(neg:SF (match_operand:SF 3 "register_operand" "r")))))]
(neg:SF (match_operand:SF 3 "register_operand" "0")))))]
"TARGET_USE_FPU"
"nmsubf.s %2,%1,%3,%0"
{ return TARGET_V850E3V5_UP ? "fnmsf.s %1, %2, %0" : "nmsubf.s %2, %1, %3, %0"; }
[(set_attr "length" "4")
(set_attr "cc" "none_0hit")
(set_attr "type" "fpu")])