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re PR rtl-optimization/13724 (Bad code generated for unsigned int -> long long multiplication)
2004-01-22 Paolo Bonzini <bonzini@gnu.org> PR optimization/13724 * cse.c (fold_rtx) <SUBREG>: Fold a SUBREG to zero if it represents the zero bits produced by a ZERO_EXTEND operation. From-SVN: r76394
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Paolo Bonzini
Roger Sayle
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commit
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@ -1,3 +1,9 @@
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2004-01-22 Paolo Bonzini <bonzini@gnu.org>
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PR optimization/13724
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* cse.c (fold_rtx) <SUBREG>: Fold a SUBREG to zero if it
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represents the zero bits produced by a ZERO_EXTEND operation.
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2004-01-22 Roger Sayle <roger@eyesopen.com>
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PR optimization/13821
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197
gcc/cse.c
197
gcc/cse.c
@ -3353,24 +3353,8 @@ fold_rtx (rtx x, rtx insn)
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return new;
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}
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/* If this is a narrowing SUBREG and our operand is a REG, see if
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we can find an equivalence for REG that is an arithmetic operation
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in a wider mode where both operands are paradoxical SUBREGs
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from objects of our result mode. In that case, we couldn't report
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an equivalent value for that operation, since we don't know what the
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extra bits will be. But we can find an equivalence for this SUBREG
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by folding that operation is the narrow mode. This allows us to
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fold arithmetic in narrow modes when the machine only supports
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word-sized arithmetic.
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Also look for a case where we have a SUBREG whose operand is the
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same as our result. If both modes are smaller than a word, we
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are simply interpreting a register in different modes and we
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can use the inner value. */
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if (GET_CODE (folded_arg0) == REG
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&& GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (folded_arg0))
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&& subreg_lowpart_p (x))
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&& GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (folded_arg0)))
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{
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struct table_elt *elt;
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@ -3383,95 +3367,122 @@ fold_rtx (rtx x, rtx insn)
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if (elt)
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elt = elt->first_same_value;
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for (; elt; elt = elt->next_same_value)
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{
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enum rtx_code eltcode = GET_CODE (elt->exp);
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if (subreg_lowpart_p (x))
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/* If this is a narrowing SUBREG and our operand is a REG, see
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if we can find an equivalence for REG that is an arithmetic
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operation in a wider mode where both operands are paradoxical
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SUBREGs from objects of our result mode. In that case, we
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couldn-t report an equivalent value for that operation, since we
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don't know what the extra bits will be. But we can find an
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equivalence for this SUBREG by folding that operation in the
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narrow mode. This allows us to fold arithmetic in narrow modes
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when the machine only supports word-sized arithmetic.
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/* Just check for unary and binary operations. */
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if (GET_RTX_CLASS (GET_CODE (elt->exp)) == '1'
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&& GET_CODE (elt->exp) != SIGN_EXTEND
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&& GET_CODE (elt->exp) != ZERO_EXTEND
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&& GET_CODE (XEXP (elt->exp, 0)) == SUBREG
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&& GET_MODE (SUBREG_REG (XEXP (elt->exp, 0))) == mode
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&& (GET_MODE_CLASS (mode)
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== GET_MODE_CLASS (GET_MODE (XEXP (elt->exp, 0)))))
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{
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rtx op0 = SUBREG_REG (XEXP (elt->exp, 0));
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Also look for a case where we have a SUBREG whose operand
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is the same as our result. If both modes are smaller
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than a word, we are simply interpreting a register in
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different modes and we can use the inner value. */
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if (GET_CODE (op0) != REG && ! CONSTANT_P (op0))
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op0 = fold_rtx (op0, NULL_RTX);
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for (; elt; elt = elt->next_same_value)
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{
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enum rtx_code eltcode = GET_CODE (elt->exp);
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op0 = equiv_constant (op0);
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if (op0)
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new = simplify_unary_operation (GET_CODE (elt->exp), mode,
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op0, mode);
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}
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else if ((GET_RTX_CLASS (GET_CODE (elt->exp)) == '2'
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|| GET_RTX_CLASS (GET_CODE (elt->exp)) == 'c')
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&& eltcode != DIV && eltcode != MOD
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&& eltcode != UDIV && eltcode != UMOD
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&& eltcode != ASHIFTRT && eltcode != LSHIFTRT
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&& eltcode != ROTATE && eltcode != ROTATERT
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&& ((GET_CODE (XEXP (elt->exp, 0)) == SUBREG
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&& (GET_MODE (SUBREG_REG (XEXP (elt->exp, 0)))
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== mode))
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|| CONSTANT_P (XEXP (elt->exp, 0)))
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&& ((GET_CODE (XEXP (elt->exp, 1)) == SUBREG
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&& (GET_MODE (SUBREG_REG (XEXP (elt->exp, 1)))
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== mode))
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|| CONSTANT_P (XEXP (elt->exp, 1))))
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{
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rtx op0 = gen_lowpart_common (mode, XEXP (elt->exp, 0));
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rtx op1 = gen_lowpart_common (mode, XEXP (elt->exp, 1));
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/* Just check for unary and binary operations. */
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if (GET_RTX_CLASS (GET_CODE (elt->exp)) == '1'
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&& GET_CODE (elt->exp) != SIGN_EXTEND
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&& GET_CODE (elt->exp) != ZERO_EXTEND
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&& GET_CODE (XEXP (elt->exp, 0)) == SUBREG
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&& GET_MODE (SUBREG_REG (XEXP (elt->exp, 0))) == mode
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&& (GET_MODE_CLASS (mode)
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== GET_MODE_CLASS (GET_MODE (XEXP (elt->exp, 0)))))
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{
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rtx op0 = SUBREG_REG (XEXP (elt->exp, 0));
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if (op0 && GET_CODE (op0) != REG && ! CONSTANT_P (op0))
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op0 = fold_rtx (op0, NULL_RTX);
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if (GET_CODE (op0) != REG && ! CONSTANT_P (op0))
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op0 = fold_rtx (op0, NULL_RTX);
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if (op0)
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op0 = equiv_constant (op0);
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if (op0)
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new = simplify_unary_operation (GET_CODE (elt->exp), mode,
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op0, mode);
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}
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else if ((GET_RTX_CLASS (GET_CODE (elt->exp)) == '2'
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|| GET_RTX_CLASS (GET_CODE (elt->exp)) == 'c')
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&& eltcode != DIV && eltcode != MOD
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&& eltcode != UDIV && eltcode != UMOD
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&& eltcode != ASHIFTRT && eltcode != LSHIFTRT
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&& eltcode != ROTATE && eltcode != ROTATERT
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&& ((GET_CODE (XEXP (elt->exp, 0)) == SUBREG
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&& (GET_MODE (SUBREG_REG (XEXP (elt->exp, 0)))
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== mode))
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|| CONSTANT_P (XEXP (elt->exp, 0)))
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&& ((GET_CODE (XEXP (elt->exp, 1)) == SUBREG
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&& (GET_MODE (SUBREG_REG (XEXP (elt->exp, 1)))
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== mode))
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|| CONSTANT_P (XEXP (elt->exp, 1))))
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{
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rtx op0 = gen_lowpart_common (mode, XEXP (elt->exp, 0));
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rtx op1 = gen_lowpart_common (mode, XEXP (elt->exp, 1));
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if (op1 && GET_CODE (op1) != REG && ! CONSTANT_P (op1))
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op1 = fold_rtx (op1, NULL_RTX);
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if (op0 && GET_CODE (op0) != REG && ! CONSTANT_P (op0))
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op0 = fold_rtx (op0, NULL_RTX);
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if (op1)
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op1 = equiv_constant (op1);
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if (op0)
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op0 = equiv_constant (op0);
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/* If we are looking for the low SImode part of
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(ashift:DI c (const_int 32)), it doesn't work
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to compute that in SImode, because a 32-bit shift
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in SImode is unpredictable. We know the value is 0. */
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if (op0 && op1
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&& GET_CODE (elt->exp) == ASHIFT
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&& GET_CODE (op1) == CONST_INT
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&& INTVAL (op1) >= GET_MODE_BITSIZE (mode))
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{
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if (INTVAL (op1) < GET_MODE_BITSIZE (GET_MODE (elt->exp)))
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if (op1 && GET_CODE (op1) != REG && ! CONSTANT_P (op1))
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op1 = fold_rtx (op1, NULL_RTX);
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/* If the count fits in the inner mode's width,
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but exceeds the outer mode's width,
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the value will get truncated to 0
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by the subreg. */
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new = const0_rtx;
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else
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/* If the count exceeds even the inner mode's width,
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if (op1)
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op1 = equiv_constant (op1);
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/* If we are looking for the low SImode part of
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(ashift:DI c (const_int 32)), it doesn't work
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to compute that in SImode, because a 32-bit shift
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in SImode is unpredictable. We know the value is 0. */
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if (op0 && op1
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&& GET_CODE (elt->exp) == ASHIFT
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&& GET_CODE (op1) == CONST_INT
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&& INTVAL (op1) >= GET_MODE_BITSIZE (mode))
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{
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if (INTVAL (op1)
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< GET_MODE_BITSIZE (GET_MODE (elt->exp)))
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/* If the count fits in the inner mode's width,
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but exceeds the outer mode's width,
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the value will get truncated to 0
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by the subreg. */
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new = CONST0_RTX (mode);
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else
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/* If the count exceeds even the inner mode's width,
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don't fold this expression. */
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new = 0;
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}
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else if (op0 && op1)
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new = simplify_binary_operation (GET_CODE (elt->exp), mode,
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op0, op1);
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}
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new = 0;
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}
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else if (op0 && op1)
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new = simplify_binary_operation (GET_CODE (elt->exp), mode, op0, op1);
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}
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else if (GET_CODE (elt->exp) == SUBREG
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&& GET_MODE (SUBREG_REG (elt->exp)) == mode
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&& (GET_MODE_SIZE (GET_MODE (folded_arg0))
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<= UNITS_PER_WORD)
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&& exp_equiv_p (elt->exp, elt->exp, 1, 0))
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new = copy_rtx (SUBREG_REG (elt->exp));
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else if (GET_CODE (elt->exp) == SUBREG
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&& GET_MODE (SUBREG_REG (elt->exp)) == mode
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&& (GET_MODE_SIZE (GET_MODE (folded_arg0))
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<= UNITS_PER_WORD)
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&& exp_equiv_p (elt->exp, elt->exp, 1, 0))
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new = copy_rtx (SUBREG_REG (elt->exp));
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if (new)
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return new;
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}
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if (new)
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return new;
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}
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else
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/* A SUBREG resulting from a zero extension may fold to zero if
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it extracts higher bits than the ZERO_EXTEND's source bits.
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FIXME: if combine tried to, er, combine these instructions,
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this transformation may be moved to simplify_subreg. */
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for (; elt; elt = elt->next_same_value)
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{
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if (GET_CODE (elt->exp) == ZERO_EXTEND
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&& subreg_lsb (x)
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>= GET_MODE_BITSIZE (GET_MODE (XEXP (elt->exp, 0))))
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return CONST0_RTX (mode);
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}
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}
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return x;
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