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rs6000.md: Change many instances of '!
* config/rs6000/rs6000.md: Change many instances of '! TARGET_POWERPC64' to 'TARGET_32BIT' when the pattern being guarded was guarded only because it changed CR0 or the carry bit in XER. From-SVN: r74966
This commit is contained in:
Geoffrey Keating
Geoffrey Keating
parent
d38d4e5d18
commit
4b8a63d6c2
@ -1,3 +1,9 @@
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2003-12-22 Geoffrey Keating <geoffk@apple.com>
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* config/rs6000/rs6000.md: Change many instances of '!
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TARGET_POWERPC64' to 'TARGET_32BIT' when the pattern being guarded
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was guarded only because it changed CR0 or the carry bit in XER.
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2003-12-23 Eric Botcazou <ebotcazou@libertysurf.fr>
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PR optimization/13394
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@ -1020,7 +1020,7 @@
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(match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=r,r,r,r"))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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{cax.|add.} %3,%1,%2
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{ai.|addic.} %3,%1,%2
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@ -1035,7 +1035,7 @@
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(match_operand:SI 2 "reg_or_short_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 3 ""))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 3)
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(plus:SI (match_dup 1)
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(match_dup 2)))
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@ -1052,7 +1052,7 @@
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
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(plus:SI (match_dup 1)
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(match_dup 2)))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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{cax.|add.} %0,%1,%2
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{ai.|addic.} %0,%1,%2
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@ -1068,7 +1068,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(plus:SI (match_dup 1) (match_dup 2)))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 0)
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(plus:SI (match_dup 1)
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(match_dup 2)))
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@ -1109,7 +1109,7 @@
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(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:SI 2 "=r,r"))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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nor. %2,%1,%1
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#"
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@ -1121,7 +1121,7 @@
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(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 2 ""))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 2)
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(not:SI (match_dup 1)))
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(set (match_dup 0)
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@ -1135,7 +1135,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(not:SI (match_dup 1)))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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nor. %0,%1,%1
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#"
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@ -1148,7 +1148,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(not:SI (match_dup 1)))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 0)
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(not:SI (match_dup 1)))
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(set (match_dup 2)
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@ -1191,7 +1191,7 @@
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(match_operand:SI 2 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=r,r"))]
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"TARGET_POWERPC && ! TARGET_POWERPC64"
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"TARGET_POWERPC && TARGET_32BIT"
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"@
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subf. %3,%2,%1
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#"
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@ -1204,7 +1204,7 @@
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(match_operand:SI 2 "gpc_reg_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 3 ""))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 3)
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(minus:SI (match_dup 1)
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(match_dup 2)))
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@ -1235,7 +1235,7 @@
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(minus:SI (match_dup 1)
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(match_dup 2)))]
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"TARGET_POWERPC && ! TARGET_POWERPC64"
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"TARGET_POWERPC && TARGET_32BIT"
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"@
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subf. %0,%2,%1
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#"
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@ -1250,7 +1250,7 @@
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(minus:SI (match_dup 1)
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(match_dup 2)))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 0)
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(minus:SI (match_dup 1)
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(match_dup 2)))
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@ -1563,7 +1563,7 @@
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(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(clobber (match_scratch:SI 2 "=r,r"))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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neg. %2,%1
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#"
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@ -1575,7 +1575,7 @@
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(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 2 ""))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 2)
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(neg:SI (match_dup 1)))
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(set (match_dup 0)
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@ -1589,7 +1589,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(neg:SI (match_dup 1)))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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neg. %0,%1
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#"
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@ -1602,7 +1602,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(neg:SI (match_dup 1)))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 0)
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(neg:SI (match_dup 1)))
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(set (match_dup 2)
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@ -2225,7 +2225,7 @@
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
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(clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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and. %3,%1,%2
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{andil.|andi.} %3,%1,%b2
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@ -2304,7 +2304,7 @@
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(and:SI (match_dup 1)
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(match_dup 2)))
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(clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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and. %0,%1,%2
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{andil.|andi.} %0,%1,%b2
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@ -2516,7 +2516,7 @@
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(match_operand:SI 2 "gpc_reg_operand" "r,r")])
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=r,r"))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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%q4. %3,%1,%2
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#"
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@ -2530,7 +2530,7 @@
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(match_operand:SI 2 "gpc_reg_operand" "")])
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(const_int 0)))
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(clobber (match_scratch:SI 3 ""))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 3) (match_dup 4))
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(set (match_dup 0)
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(compare:CC (match_dup 3)
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@ -2545,7 +2545,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(match_dup 4))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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%q4. %0,%1,%2
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#"
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@ -2560,7 +2560,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(match_dup 4))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 0) (match_dup 4))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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@ -2604,7 +2604,7 @@
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(match_operand:SI 2 "gpc_reg_operand" "r,r")])
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=r,r"))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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%q4. %3,%2,%1
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#"
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@ -2618,7 +2618,7 @@
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(match_operand:SI 2 "gpc_reg_operand" "")])
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(const_int 0)))
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(clobber (match_scratch:SI 3 ""))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 3) (match_dup 4))
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(set (match_dup 0)
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(compare:CC (match_dup 3)
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@ -2633,7 +2633,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(match_dup 4))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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%q4. %0,%2,%1
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#"
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@ -2648,7 +2648,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(match_dup 4))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 0) (match_dup 4))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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@ -2670,7 +2670,7 @@
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(not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=r,r"))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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%q4. %3,%1,%2
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#"
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@ -2684,7 +2684,7 @@
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(not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
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(const_int 0)))
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(clobber (match_scratch:SI 3 ""))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 3) (match_dup 4))
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(set (match_dup 0)
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(compare:CC (match_dup 3)
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@ -2699,7 +2699,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(match_dup 4))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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%q4. %0,%1,%2
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#"
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@ -2714,7 +2714,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(match_dup 4))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 0) (match_dup 4))
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(set (match_dup 3)
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(compare:CC (match_dup 0)
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@ -3618,7 +3618,7 @@
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(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=r,r"))]
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"! TARGET_POWER && ! TARGET_POWERPC64"
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"! TARGET_POWER && TARGET_32BIT"
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"@
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{sl|slw}%I2. %3,%1,%h2
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#"
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@ -3631,7 +3631,7 @@
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(match_operand:SI 2 "reg_or_cint_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 3 ""))]
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"! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
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"! TARGET_POWER && TARGET_32BIT && reload_completed"
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[(set (match_dup 3)
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(ashift:SI (match_dup 1) (match_dup 2)))
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(set (match_dup 0)
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@ -3680,7 +3680,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(ashift:SI (match_dup 1) (match_dup 2)))]
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"! TARGET_POWER && ! TARGET_POWERPC64"
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"! TARGET_POWER && TARGET_32BIT"
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"@
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{sl|slw}%I2. %0,%1,%h2
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#"
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@ -3694,7 +3694,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(ashift:SI (match_dup 1) (match_dup 2)))]
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"! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
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"! TARGET_POWER && TARGET_32BIT && reload_completed"
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[(set (match_dup 0)
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(ashift:SI (match_dup 1) (match_dup 2)))
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(set (match_dup 3)
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@ -3851,7 +3851,7 @@
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(match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=X,r,X,r"))]
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"! TARGET_POWER && ! TARGET_POWERPC64"
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"! TARGET_POWER && TARGET_32BIT"
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"@
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mr. %1,%1
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{sr|srw}%I2. %3,%1,%h2
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@ -3866,7 +3866,7 @@
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(match_operand:SI 2 "reg_or_cint_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 3 ""))]
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"! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
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"! TARGET_POWER && TARGET_32BIT && reload_completed"
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[(set (match_dup 3)
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(lshiftrt:SI (match_dup 1) (match_dup 2)))
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(set (match_dup 0)
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@ -3917,7 +3917,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
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(lshiftrt:SI (match_dup 1) (match_dup 2)))]
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"! TARGET_POWER && ! TARGET_POWERPC64"
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"! TARGET_POWER && TARGET_32BIT"
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"@
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mr. %0,%1
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{sr|srw}%I2. %0,%1,%h2
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@ -3933,7 +3933,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(lshiftrt:SI (match_dup 1) (match_dup 2)))]
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"! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
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"! TARGET_POWER && TARGET_32BIT && reload_completed"
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[(set (match_dup 0)
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(lshiftrt:SI (match_dup 1) (match_dup 2)))
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(set (match_dup 3)
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@ -7739,7 +7739,7 @@
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(compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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{cmpi|cmpwi} %2,%0,0
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mr. %0,%1
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@ -7752,7 +7752,7 @@
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(compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 0) (match_dup 1))
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(set (match_dup 2)
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(compare:CC (match_dup 0)
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@ -11286,7 +11286,7 @@
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(const_int 0)))
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(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
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(match_op_dup 1 [(match_dup 2) (const_int 0)]))]
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"! TARGET_POWERPC64"
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"TARGET_32BIT"
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"@
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mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
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#"
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@ -11301,7 +11301,7 @@
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(const_int 0)))
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(set (match_operand:SI 3 "gpc_reg_operand" "")
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(match_op_dup 1 [(match_dup 2) (const_int 0)]))]
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"! TARGET_POWERPC64 && reload_completed"
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 3)
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(match_op_dup 1 [(match_dup 2) (const_int 0)]))
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(set (match_dup 0)
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@ -12018,7 +12018,7 @@
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
(leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
|
||||
"! TARGET_POWERPC64"
|
||||
"TARGET_32BIT"
|
||||
"{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
|
||||
[(set_attr "length" "12")])
|
||||
|
||||
@ -14169,7 +14169,7 @@
|
||||
(const_int -1)))
|
||||
(clobber (match_scratch:CC 3 ""))
|
||||
(clobber (match_scratch:SI 4 ""))]
|
||||
"! TARGET_POWERPC64 && reload_completed"
|
||||
"TARGET_32BIT && reload_completed"
|
||||
[(parallel [(set (match_dup 3)
|
||||
(compare:CC (plus:SI (match_dup 1)
|
||||
(const_int -1))
|
||||
@ -14195,7 +14195,7 @@
|
||||
(plus:SI (match_dup 1) (const_int -1)))
|
||||
(clobber (match_scratch:CC 3 ""))
|
||||
(clobber (match_scratch:SI 4 ""))]
|
||||
"! TARGET_POWERPC64 && reload_completed
|
||||
"TARGET_32BIT && reload_completed
|
||||
&& ! gpc_reg_operand (operands[0], SImode)"
|
||||
[(parallel [(set (match_dup 3)
|
||||
(compare:CC (plus:SI (match_dup 1)
|
||||
@ -14267,63 +14267,6 @@
|
||||
"
|
||||
{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
|
||||
const0_rtx); }")
|
||||
|
||||
; These two are for 64-bit hardware running 32-bit mode.
|
||||
; We don't use the add. instruction in this mode.
|
||||
(define_split
|
||||
[(set (pc)
|
||||
(if_then_else (match_operator 2 "comparison_operator"
|
||||
[(match_operand:SI 1 "gpc_reg_operand" "")
|
||||
(const_int 1)])
|
||||
(match_operand 5 "" "")
|
||||
(match_operand 6 "" "")))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "")
|
||||
(plus:SI (match_dup 1)
|
||||
(const_int -1)))
|
||||
(clobber (match_scratch:CC 3 ""))
|
||||
(clobber (match_scratch:SI 4 ""))]
|
||||
"TARGET_POWERPC64 && TARGET_32BIT && reload_completed"
|
||||
[(set (match_dup 0)
|
||||
(plus:SI (match_dup 1)
|
||||
(const_int -1)))
|
||||
(set (match_dup 3)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))
|
||||
(set (pc) (if_then_else (match_dup 7)
|
||||
(match_dup 5)
|
||||
(match_dup 6)))]
|
||||
"
|
||||
{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
|
||||
const0_rtx); }")
|
||||
|
||||
(define_split
|
||||
[(set (pc)
|
||||
(if_then_else (match_operator 2 "comparison_operator"
|
||||
[(match_operand:SI 1 "gpc_reg_operand" "")
|
||||
(const_int 1)])
|
||||
(match_operand 5 "" "")
|
||||
(match_operand 6 "" "")))
|
||||
(set (match_operand:SI 0 "nonimmediate_operand" "")
|
||||
(plus:SI (match_dup 1) (const_int -1)))
|
||||
(clobber (match_scratch:CC 3 ""))
|
||||
(clobber (match_scratch:SI 4 ""))]
|
||||
"TARGET_POWERPC64 && TARGET_32BIT && reload_completed
|
||||
&& ! gpc_reg_operand (operands[0], SImode)"
|
||||
[(set (match_dup 4)
|
||||
(plus:SI (match_dup 1)
|
||||
(const_int -1)))
|
||||
(set (match_dup 3)
|
||||
(compare:CC (match_dup 4)
|
||||
(const_int 0)))
|
||||
(set (match_dup 0)
|
||||
(match_dup 4))
|
||||
(set (pc) (if_then_else (match_dup 7)
|
||||
(match_dup 5)
|
||||
(match_dup 6)))]
|
||||
"
|
||||
{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
|
||||
const0_rtx); }")
|
||||
|
||||
|
||||
(define_insn "trap"
|
||||
[(trap_if (const_int 1) (const_int 0))]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user