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LoongArch Port: gcc/testsuite
2022-03-29 Chenghua Xu <xuchenghua@loongson.cn> Lulu Cheng <chenglulu@loongson.cn> gcc/testsuite/ChangeLog: * g++.dg/cpp0x/constexpr-rom.C: Add build options for LoongArch. * g++.old-deja/g++.abi/ptrmem.C: Add LoongArch support. * g++.old-deja/g++.pt/ptrmem6.C: xfail for LoongArch. * gcc.dg/20020312-2.c: Add LoongArch support. * c-c++-common/zero-scratch-regs-10.c: Like wise * c-c++-common/zero-scratch-regs-11.c: Like wise * c-c++-common/zero-scratch-regs-8.c: Like wise * c-c++-common/zero-scratch-regs-9.c: Like wise * gcc.dg/loop-8.c: Skip on LoongArch. * gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise. * gcc.dg/tree-ssa/ssa-fre-3.c: Likewise. * go.test/go-test.exp: Define the LoongArch target. * lib/target-supports.exp: Like wise. * gcc.target/loongarch/loongarch.exp: New file. * gcc.target/loongarch/tst-asm-const.c: Like wise. * gcc.target/loongarch/larch-builtin.c: Like wise.
This commit is contained in:
chenglulu
Chenghua Xu
parent
34024b7150
commit
4ae54e8dec
@ -1,5 +1,5 @@
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/* { dg-do run } */
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/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* nvptx*-*-* s390*-*-* } } } */
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/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* nvptx*-*-* s390*-*-* loongarch64*-*-* } } } */
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/* { dg-options "-O2" } */
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#include <assert.h>
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@ -1,5 +1,5 @@
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/* { dg-do run } */
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/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* } } } */
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/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* loongarch64*-*-* } } } */
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/* { dg-options "-O2 -fzero-call-used-regs=all" } */
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#include "zero-scratch-regs-10.c"
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@ -1,5 +1,5 @@
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/* { dg-do run } */
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/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* } } } */
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/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* loongarch64*-*-* } } } */
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/* { dg-options "-O2 -fzero-call-used-regs=all-arg" } */
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#include "zero-scratch-regs-1.c"
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@ -1,5 +1,5 @@
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/* { dg-do run } */
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/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* } } } */
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/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* loongarch64*-*-* } } } */
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/* { dg-options "-O2 -fzero-call-used-regs=all" } */
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#include "zero-scratch-regs-1.c"
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@ -1,6 +1,6 @@
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// PR c++/49673: check that test_data goes into .rodata
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// { dg-do compile { target c++11 } }
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// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* nios2-*-* powerpc*-*-* rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } }
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// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* loongarch*-*-* nios2-*-* powerpc*-*-* rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } }
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// { dg-final { scan-assembler "\\.rdata" { target mips*-*-* } } }
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// { dg-final { scan-assembler "rodata" { target { { *-*-linux-gnu *-*-gnu* *-*-elf } && { ! { mips*-*-* riscv*-*-* } } } } } }
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@ -7,7 +7,7 @@
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function. However, some platforms use all bits to encode a
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function pointer. Such platforms use the lowest bit of the delta,
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that is shifted left by one bit. */
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#if defined __MN10300__ || defined __SH5__ || defined __arm__ || defined __thumb__ || defined __mips__ || defined __aarch64__ || defined __PRU__
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#if defined __MN10300__ || defined __SH5__ || defined __arm__ || defined __thumb__ || defined __mips__ || defined __aarch64__ || defined __PRU__ || defined __loongarch__
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#define ADJUST_PTRFN(func, virt) ((void (*)())(func))
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#define ADJUST_DELTA(delta, virt) (((delta) << 1) + !!(virt))
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#else
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@ -25,7 +25,7 @@ int main() {
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h<&B::j>(); // { dg-error "" }
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g<(void (A::*)()) &A::f>(); // { dg-error "" "" { xfail c++11 } }
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h<(int A::*) &A::i>(); // { dg-error "" "" { xfail c++11 } }
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g<(void (A::*)()) &B::f>(); // { dg-error "" "" { xfail { c++11 && { aarch64*-*-* arm*-*-* mips*-*-* } } } }
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g<(void (A::*)()) &B::f>(); // { dg-error "" "" { xfail { c++11 && { aarch64*-*-* arm*-*-* mips*-*-* loongarch*-*-* } } } }
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h<(int A::*) &B::j>(); // { dg-error "" }
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g<(void (A::*)()) 0>(); // { dg-error "" "" { target { ! c++11 } } }
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h<(int A::*) 0>(); // { dg-error "" "" { target { ! c++11 } } }
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@ -37,6 +37,8 @@ extern void abort (void);
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/* PIC register is r1, but is used even without -fpic. */
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#elif defined(__lm32__)
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/* No pic register. */
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#elif defined(__loongarch__)
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/* No pic register. */
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#elif defined(__M32R__)
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/* No pic register. */
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#elif defined(__m68k__)
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@ -1,6 +1,6 @@
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/* { dg-do compile } */
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/* { dg-options "-O1 -fdump-rtl-loop2_invariant" } */
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/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-* powerpc*-*-* riscv*-*-* mmix-*-* vax-*-*" } } */
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/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-* powerpc*-*-* riscv*-*-* mmix-*-* vax-*-* loongarch*-*-*" } } */
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/* Load immediate on condition is available from z13 on and prevents moving
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the load out of the loop, so always run this test with -march=zEC12 that
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does not have load immediate on condition. */
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@ -9,7 +9,7 @@
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/* arm_hf_eabi: Variadic funcs use Base AAPCS. Normal funcs use VFP variant.
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avr: Variadic funcs don't pass arguments in registers, while normal funcs
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do. */
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/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { csky*-*-* avr-*-* riscv*-*-* or1k*-*-* msp430-*-* amdgcn-*-* pru-*-* } } } */
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/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { csky*-*-* avr-*-* riscv*-*-* or1k*-*-* msp430-*-* amdgcn-*-* pru-*-* loongarch*-*-* } } } */
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/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { nds32*-*-* } { v850*-*-* } } */
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/* { dg-require-effective-target untyped_assembly } */
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@ -5,7 +5,7 @@
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When the condition is true, we distribute "(int) (a + b)" as
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"(int) a + (int) b", otherwise we keep the original. */
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/* { dg-do compile { target { ! mips64 } } } */
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/* { dg-do compile { target { ! mips64 } && { ! loongarch64 } } } */
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/* { dg-options "-O -fno-tree-forwprop -fno-tree-ccp -fwrapv -fdump-tree-fre1-details" } */
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/* From PR14844. */
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265
gcc/testsuite/gcc.target/loongarch/larch-builtin.c
Normal file
265
gcc/testsuite/gcc.target/loongarch/larch-builtin.c
Normal file
@ -0,0 +1,265 @@
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/* Test for LoongArch intrinsics. */
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/* { dg-do compile } */
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/* { dg-final { scan-assembler-times "test_rdtime_d:.*rdtime\\.d.*\\.size test_rdtime_d" 1 } } */
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/* { dg-final { scan-assembler-times "test_rdtimeh_w:.*rdtimeh\\.w.*\\.size test_rdtimeh_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_rdtimel_w:.*rdtimel\\.w.*\\.size test_rdtimel_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_movfcsr2gr:.*movfcsr2gr.*\\.size test_movfcsr2gr" 1 } } */
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/* { dg-final { scan-assembler-times "test_movgr2fcsr:.*movgr2fcsr.*\\.size test_movgr2fcsr" 1 } } */
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/* { dg-final { scan-assembler-times "test_cacop_d:.*cacop.*\\.size test_cacop_d" 1 } } */
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/* { dg-final { scan-assembler-times "test_cpucfg:.*cpucfg.*\\.size test_cpucfg" 1 } } */
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/* { dg-final { scan-assembler-times "test_asrtle_d:.*asrtle\\.d.*\\.size test_asrtle_d" 1 } } */
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/* { dg-final { scan-assembler-times "test_asrtgt_d:.*asrtgt\\.d.*\\.size test_asrtgt_d" 1 } } */
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/* { dg-final { scan-assembler-times "test_lddir_d:.*lddir.*\\.size test_lddir_d" 1 } } */
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/* { dg-final { scan-assembler-times "test_ldpte_d:.*ldpte.*\\.size test_ldpte_d" 1 } } */
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/* { dg-final { scan-assembler-times "test_crc_w_b_w:.*crc\\.w\\.b\\.w.*\\.size test_crc_w_b_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_crc_w_h_w:.*crc\\.w\\.h\\.w.*\\.size test_crc_w_h_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_crc_w_w_w:.*crc\\.w\\.w\\.w.*\\.size test_crc_w_w_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_crc_w_d_w:.*crc\\.w\\.d\\.w.*\\.size test_crc_w_d_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_crcc_w_b_w:.*crcc\\.w\\.b\\.w.*\\.size test_crcc_w_b_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_crcc_w_h_w:.*crcc\\.w\\.h\\.w.*\\.size test_crcc_w_h_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_crcc_w_w_w:.*crcc\\.w\\.w\\.w.*\\.size test_crcc_w_w_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_crcc_w_d_w:.*crcc\\.w\\.d\\.w.*\\.size test_crcc_w_d_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_csrrd_w:.*csrrd.*\\.size test_csrrd_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_csrwr_w:.*csrwr.*\\.size test_csrwr_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_csrxchg_w:.*csrxchg.*\\.size test_csrxchg_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_csrrd_d:.*csrrd.*\\.size test_csrrd_d" 1 } } */
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/* { dg-final { scan-assembler-times "test_csrwr_d:.*csrwr.*\\.size test_csrwr_d" 1 } } */
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/* { dg-final { scan-assembler-times "test_csrxchg_d:.*csrxchg.*\\.size test_csrxchg_d" 1 } } */
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/* { dg-final { scan-assembler-times "test_iocsrrd_b:.*iocsrrd\\.b.*\\.size test_iocsrrd_b" 1 } } */
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/* { dg-final { scan-assembler-times "test_iocsrrd_h:.*iocsrrd\\.h.*\\.size test_iocsrrd_h" 1 } } */
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/* { dg-final { scan-assembler-times "test_iocsrrd_w:.*iocsrrd\\.w.*\\.size test_iocsrrd_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_iocsrrd_d:.*iocsrrd\\.d.*\\.size test_iocsrrd_d" 1 } } */
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/* { dg-final { scan-assembler-times "test_iocsrwr_b:.*iocsrwr\\.b.*\\.size test_iocsrwr_b" 1 } } */
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/* { dg-final { scan-assembler-times "test_iocsrwr_h:.*iocsrwr\\.h.*\\.size test_iocsrwr_h" 1 } } */
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/* { dg-final { scan-assembler-times "test_iocsrwr_w:.*iocsrwr\\.w.*\\.size test_iocsrwr_w" 1 } } */
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/* { dg-final { scan-assembler-times "test_iocsrwr_d:.*iocsrwr\\.d.*\\.size test_iocsrwr_d" 1 } } */
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/* { dg-final { scan-assembler-times "test_dbar:.*dbar.*\\.size test_dbar" 1 } } */
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/* { dg-final { scan-assembler-times "test_ibar:.*ibar.*\\.size test_ibar" 1 } } */
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/* { dg-final { scan-assembler-times "test_syscall:.*syscall.*\\.size test_syscall" 1 } } */
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/* { dg-final { scan-assembler-times "test_break:.*break.*\\.size test_break" 1 } } */
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#include<larchintrin.h>
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__drdtime_t
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test_rdtime_d ()
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{
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return __rdtime_d ();
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}
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__rdtime_t
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test_rdtimeh_w ()
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{
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return __rdtimeh_w ();
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}
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__rdtime_t
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test_rdtimel_w ()
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{
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return __rdtimel_w ();
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}
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unsigned int
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test_movfcsr2gr ()
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{
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return __movfcsr2gr (1);
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}
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void
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test_movgr2fcsr (unsigned int _1)
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{
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__movgr2fcsr (1, _1);
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}
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void
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test_cacop_d (unsigned long int _1)
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{
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__cacop_d (1, _1, 1);
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}
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unsigned int
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test_cpucfg (unsigned int _1)
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{
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return __cpucfg (_1);
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}
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void
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test_asrtle_d (long int _1, long int _2)
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{
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__asrtle_d (_1, _2);
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}
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void
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test_asrtgt_d (long int _1, long int _2)
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{
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__asrtgt_d (_1, _2);
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}
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long int
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test_lddir_d (long int _1)
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{
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return __lddir_d (_1, 1);
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}
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void
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test_ldpte_d (long int _1)
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{
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__ldpte_d (_1, 1);
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}
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int
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test_crc_w_b_w (char _1, int _2)
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{
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return __crc_w_b_w (_1, _2);
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}
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int
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test_crc_w_h_w (short _1, int _2)
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{
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return __crc_w_h_w (_1, _2);
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}
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int
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test_crc_w_w_w (int _1, int _2)
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{
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return __crc_w_w_w (_1, _2);
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}
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int
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test_crc_w_d_w (long int _1, int _2)
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{
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return __crc_w_d_w (_1, _2);
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}
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int
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test_crcc_w_b_w (char _1, int _2)
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{
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return __crcc_w_b_w (_1, _2);
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}
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int
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test_crcc_w_h_w (short _1, int _2)
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{
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return __crcc_w_h_w (_1, _2);
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}
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int
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test_crcc_w_w_w (int _1, int _2)
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{
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return __crcc_w_w_w (_1, _2);
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}
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int
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test_crcc_w_d_w (long int _1, int _2)
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{
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return __crcc_w_d_w (_1, _2);
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}
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unsigned int
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test_csrrd_w ()
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{
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return __csrrd_w (1);
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}
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unsigned int
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test_csrwr_w (unsigned int _1)
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{
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return __csrwr_w (_1, 1);
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}
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unsigned int
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test_csrxchg_w (unsigned int _1, unsigned int _2)
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{
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return __csrxchg_w (_1, _2, 1);
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}
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unsigned long int
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test_csrrd_d ()
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{
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return __csrrd_d (1);
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}
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unsigned long int
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test_csrwr_d (unsigned long int _1)
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{
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return __csrwr_d (_1, 1);
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}
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unsigned long int
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test_csrxchg_d (unsigned long int _1, unsigned long int _2)
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{
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return __csrxchg_d (_1, _2, 1);
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}
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unsigned char
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test_iocsrrd_b (unsigned int _1)
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{
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return __iocsrrd_b (_1);
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}
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unsigned char
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test_iocsrrd_h (unsigned int _1)
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{
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return __iocsrrd_h (_1);
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}
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unsigned int
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test_iocsrrd_w (unsigned int _1)
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{
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return __iocsrrd_w (_1);
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}
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unsigned long int
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test_iocsrrd_d (unsigned int _1)
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{
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return __iocsrrd_d (_1);
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}
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void
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test_iocsrwr_b (unsigned char _1, unsigned int _2)
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{
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__iocsrwr_b (_1, _2);
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}
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void
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test_iocsrwr_h (unsigned short _1, unsigned int _2)
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{
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__iocsrwr_h (_1, _2);
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}
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||||
void
|
||||
test_iocsrwr_w (unsigned int _1, unsigned int _2)
|
||||
{
|
||||
__iocsrwr_w (_1, _2);
|
||||
}
|
||||
|
||||
void
|
||||
test_iocsrwr_d (unsigned long int _1, unsigned int _2)
|
||||
{
|
||||
__iocsrwr_d (_1, _2);
|
||||
}
|
||||
|
||||
void
|
||||
test_dbar ()
|
||||
{
|
||||
__dbar (1);
|
||||
}
|
||||
|
||||
void
|
||||
test_ibar ()
|
||||
{
|
||||
__ibar (1);
|
||||
}
|
||||
|
||||
void
|
||||
test_syscall ()
|
||||
{
|
||||
__syscall (1);
|
||||
}
|
||||
|
||||
void
|
||||
test_break ()
|
||||
{
|
||||
__break (1);
|
||||
}
|
||||
40
gcc/testsuite/gcc.target/loongarch/loongarch.exp
Normal file
40
gcc/testsuite/gcc.target/loongarch/loongarch.exp
Normal file
@ -0,0 +1,40 @@
|
||||
# Copyright (C) 2021-2022 Free Software Foundation, Inc.
|
||||
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with GCC; see the file COPYING3. If not see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
|
||||
# GCC testsuite that uses the `dg.exp' driver.
|
||||
|
||||
# Exit immediately if this isn't a LoongArch target.
|
||||
if ![istarget loongarch*-*-*] then {
|
||||
return
|
||||
}
|
||||
|
||||
# Load support procs.
|
||||
load_lib gcc-dg.exp
|
||||
|
||||
# If a testcase doesn't have special options, use these.
|
||||
global DEFAULT_CFLAGS
|
||||
if ![info exists DEFAULT_CFLAGS] then {
|
||||
set DEFAULT_CFLAGS " "
|
||||
}
|
||||
|
||||
# Initialize `dg'.
|
||||
dg-init
|
||||
|
||||
# Main loop.
|
||||
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
|
||||
"" $DEFAULT_CFLAGS
|
||||
# All done.
|
||||
dg-finish
|
||||
16
gcc/testsuite/gcc.target/loongarch/tst-asm-const.c
Normal file
16
gcc/testsuite/gcc.target/loongarch/tst-asm-const.c
Normal file
@ -0,0 +1,16 @@
|
||||
/* Test asm const. */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-final { scan-assembler-times "foo:.*\\.long 1061109567.*\\.long 52" 1 } } */
|
||||
int foo ()
|
||||
{
|
||||
__asm__ volatile (
|
||||
"foo:"
|
||||
"\n\t"
|
||||
".long %a0\n\t"
|
||||
".long %a1\n\t"
|
||||
:
|
||||
:"i"(0x3f3f3f3f), "i"(52)
|
||||
:
|
||||
);
|
||||
}
|
||||
|
||||
@ -232,6 +232,9 @@ proc go-set-goarch { } {
|
||||
"riscv64-*-*" {
|
||||
set goarch "riscv64"
|
||||
}
|
||||
"loongarch64-*-*" {
|
||||
set goarch "loongarch64"
|
||||
}
|
||||
"s390*-*-*" {
|
||||
if [check_effective_target_ilp32] {
|
||||
set goarch "s390"
|
||||
|
||||
@ -1297,6 +1297,14 @@ proc check_effective_target_mpaired_single { } {
|
||||
# Return true if the target has access to FPU instructions.
|
||||
|
||||
proc check_effective_target_hard_float { } {
|
||||
if { [istarget loongarch*-*-*] } {
|
||||
return [check_no_compiler_messages hard_float assembly {
|
||||
#if (defined __loongarch_soft_float)
|
||||
#error __loongarch_soft_float
|
||||
#endif
|
||||
}]
|
||||
}
|
||||
|
||||
if { [istarget mips*-*-*] } {
|
||||
return [check_no_compiler_messages hard_float assembly {
|
||||
#if (defined __mips_soft_float || defined __mips16)
|
||||
@ -8616,6 +8624,7 @@ proc check_effective_target_sync_char_short { } {
|
||||
|| [istarget cris-*-*]
|
||||
|| ([istarget sparc*-*-*] && [check_effective_target_sparc_v9])
|
||||
|| ([istarget arc*-*-*] && [check_effective_target_arc_atomic])
|
||||
|| [istarget loongarch*-*-*]
|
||||
|| [check_effective_target_mips_llsc] }}]
|
||||
}
|
||||
|
||||
@ -10708,6 +10717,7 @@ proc check_effective_target_branch_cost {} {
|
||||
|| [istarget epiphany*-*-*]
|
||||
|| [istarget frv*-*-*]
|
||||
|| [istarget i?86-*-*] || [istarget x86_64-*-*]
|
||||
|| [istarget loongarch*-*-*]
|
||||
|| [istarget mips*-*-*]
|
||||
|| [istarget s390*-*-*]
|
||||
|| [istarget riscv*-*-*]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user