mirror/gcc
2
0
Fork 0
mirror of git://gcc.gnu.org/git/gcc.git synced 2025-04-05 10:50:51 +08:00
Code Issues Packages Projects Releases Wiki Activity

invoke.texi: Add cpu_type's 464 and 464fp.

Browse Source 
* doc/invoke.texi: Add cpu_type's 464 and 464fp.
	(-mmulhw): Add 464 to description.
	(-mdlmzb): Likewise.
	* config.gcc: Handle --with-cpu=464 and --with-cpu=464fp.
	* config/rs6000/rs6000.c (processor_target_table): Add 464 and
	464fp entries.
	* config/rs6000/rs6000.h (ASM_CPU_SPEC): Add 464 and 464fp support.
	* config/rs6000/t-fprules (MULTILIB_MATCHES_FLOAT): Include -mcpu=464.
	* config/rs6000/rs6000.md: Update comments for 464.

From-SVN: r135730
This commit is contained in:
Peter Bergner 2008-05-21 13:09:07 -05:00 committed by Peter Bergner
parent 00a25a2d39
commit 4adf800837
7 changed files with 27 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
gcc/ChangeLog
View File

@ -1,3 +1,15 @@
2008-05-21 Peter Bergner <bergner@vnet.ibm.com>
* doc/invoke.texi: Add cpu_type's 464 and 464fp.
(-mmulhw): Add 464 to description.
(-mdlmzb): Likewise.
* config.gcc: Handle --with-cpu=464 and --with-cpu=464fp.
* config/rs6000/rs6000.c (processor_target_table): Add 464 and
464fp entries.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Add 464 and 464fp support.
* config/rs6000/t-fprules (MULTILIB_MATCHES_FLOAT): Include -mcpu=464.
* config/rs6000/rs6000.md: Update comments for 464.
2008-05-21 Janis Johnson <janis187@us.ibm.com>
* doc/sourcebuild.texi (Test Directives): Add dg-xfail-run-if.

4
gcc/config.gcc
View File

@ -3154,8 +3154,8 @@ case "${target}" in
"" | common \
| power | power[23456] | power6x | powerpc | powerpc64 \
| rios | rios1 | rios2 | rsc | rsc1 | rs64a \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \
| 601 | 602 | 603 | 603e | ec603e | 604 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
| 505 | 601 | 602 | 603 | 603e | ec603e | 604 \
| 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \
| 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
# OK

4
gcc/config/rs6000/rs6000.c
View File

@ -1422,6 +1422,10 @@ rs6000_override_options (const char *default_cpu)
POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
{"440fp", PROCESSOR_PPC440,
POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
{"464", PROCESSOR_PPC440,
POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
{"464fp", PROCESSOR_PPC440,
POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
{"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
{"601", PROCESSOR_PPC601,
MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},

2
gcc/config/rs6000/rs6000.h
View File

@ -105,6 +105,8 @@
%{mcpu=405fp: -m405} \
%{mcpu=440: -m440} \
%{mcpu=440fp: -m440} \
%{mcpu=464: -m440} \
%{mcpu=464fp: -m440} \
%{mcpu=505: -mppc} \
%{mcpu=601: -m601} \
%{mcpu=602: -mppc} \

4
gcc/config/rs6000/rs6000.md
View File

@ -937,7 +937,7 @@
[(set_attr "type" "compare")
(set_attr "length" "4,8")])
;; IBM 405 and 440 half-word multiplication operations.
;; IBM 405, 440 and 464 half-word multiplication operations.
(define_insn "*macchwc"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
@ -1401,7 +1401,7 @@
"mullhwu %0, %1, %2"
[(set_attr "type" "imul3")])
;; IBM 405 and 440 string-search dlmzb instruction support.
;; IBM 405, 440 and 464 string-search dlmzb instruction support.
(define_insn "dlmzb"
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")

1
gcc/config/rs6000/t-fprules
View File

@ -2,6 +2,7 @@ MULTILIB_MATCHES_FLOAT = msoft-float=mcpu?401 \
msoft-float=mcpu?403 \
msoft-float=mcpu?405 \
msoft-float=mcpu?440 \
msoft-float=mcpu?464 \
msoft-float=mcpu?ec603e \
msoft-float=mcpu?801 \
msoft-float=mcpu?821 \

8
gcc/doc/invoke.texi
View File

@ -12990,8 +12990,8 @@ should normally not specify either @option{-mnew-mnemonics} or
Set architecture type, register usage, choice of mnemonics, and
instruction scheduling parameters for machine type @var{cpu_type}.
Supported values for @var{cpu_type} are @samp{401}, @samp{403},
@samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{505},
@samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
@samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{464}, @samp{464fp},
@samp{505}, @samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
@samp{860}, @samp{970}, @samp{8540}, @samp{e300c2}, @samp{e300c3},
@ -13289,7 +13289,7 @@ hardware floating is used.
@opindex mmulhw
@opindex mno-mulhw
Generate code that uses (does not use) the half-word multiply and
multiply-accumulate instructions on the IBM 405 and 440 processors.
multiply-accumulate instructions on the IBM 405, 440 and 464 processors.
These instructions are generated by default when targetting those
processors.
@ -13298,7 +13298,7 @@ processors.
@opindex mdlmzb
@opindex mno-dlmzb
Generate code that uses (does not use) the string-search @samp{dlmzb}
instruction on the IBM 405 and 440 processors. This instruction is
instruction on the IBM 405, 440 and 464 processors. This instruction is
generated by default when targetting those processors.
@item -mno-bit-align