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libatomic: Handle AVX+CX16 AMD like Intel for 16b atomics [PR104688]

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We got a response from AMD in
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688#c10
so the following patch starts treating AMD with AVX and CMPXCHG16B
ISAs like Intel by using vmovdqa for atomic load/store in libatomic.
We still don't have confirmation from Zhaoxin and VIA (anything else
with CPUs featuring AVX and CX16?).

2022-11-15  Jakub Jelinek  <jakub@redhat.com>

	PR target/104688
	* config/x86/init.c (__libat_feat1_init): Don't clear
	bit_AVX on AMD CPUs.
This commit is contained in:
Jakub Jelinek 2022-11-15 08:14:45 +01:00
parent 7cf165de63
commit 4a7a846687
1 changed files with 4 additions and 2 deletions
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6
libatomic/config/x86/init.c
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@ -39,10 +39,12 @@ __libat_feat1_init (void)
== (bit_AVX | bit_CMPXCHG16B))
{
/* Intel SDM guarantees that 16-byte VMOVDQA on 16-byte aligned address
is atomic, but so far we don't have this guarantee from AMD. */
is atomic, and AMD is going to do something similar soon.
We don't have a guarantee from vendors of other CPUs with AVX,
like Zhaoxin and VIA. */
unsigned int ecx2 = 0;
__get_cpuid (0, &eax, &ebx, &ecx2, &edx);
if (ecx2 != signature_INTEL_ecx)
if (ecx2 != signature_INTEL_ecx && ecx2 != signature_AMD_ecx)
FEAT1_REGISTER &= ~bit_AVX;
}
#endif