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[AArch64][SVE] Add missing movprfx attribute to some ternary arithmetic patterns

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The two affected SVE2 patterns in this patch output a movprfx'ed instruction in their second alternative
but don't set the "movprfx" attribute, which will result in the wrong instruction length being assumed by the midend.

This patch fixes that in the same way as the other SVE patterns in the backend.

Bootstrapped and tested on aarch64-none-linux-gnu.

2020-03-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
	Specify movprfx attribute.
	(@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.
This commit is contained in:
Kyrylo Tkachov 2020-03-06 16:21:33 +00:00
parent 3dcf51ad7b
commit 4a5c938bbf
2 changed files with 8 additions and 0 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
Specify movprfx attribute.
(@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.
2020-03-06 David Edelsohn <dje.gcc@gmail.com>
PR target/94065

2
gcc/config/aarch64/aarch64-sve2.md
View File

@ -690,6 +690,7 @@
"@
<sve_int_op>\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>
movprfx\t%0, %1\;<sve_int_op>\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>"
[(set_attr "movprfx" "*,yes")]
)
(define_insn "@aarch64_sve_<sve_int_op>_lane_<mode>"
@ -706,6 +707,7 @@
"@
<sve_int_op>\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>[%4]
movprfx\t%0, %1\;<sve_int_op>\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>[%4]"
[(set_attr "movprfx" "*,yes")]
)
;; -------------------------------------------------------------------------