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gcn: Add else operand to masked loads.
This patch adds an undefined else operand to the masked loads. gcc/ChangeLog: * config/gcn/predicates.md (maskload_else_operand): New predicate. * config/gcn/gcn-valu.md: Use new predicate.
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@ -3989,7 +3989,8 @@
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(define_expand "maskload<mode>di"
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[(match_operand:V_MOV 0 "register_operand")
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(match_operand:V_MOV 1 "memory_operand")
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(match_operand 2 "")]
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(match_operand 2 "")
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(match_operand:V_MOV 3 "maskload_else_operand")]
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""
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{
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rtx exec = force_reg (DImode, operands[2]);
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@ -3998,11 +3999,8 @@
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rtx as = gen_rtx_CONST_INT (VOIDmode, MEM_ADDR_SPACE (operands[1]));
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rtx v = gen_rtx_CONST_INT (VOIDmode, MEM_VOLATILE_P (operands[1]));
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/* Masked lanes are required to hold zero. */
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emit_move_insn (operands[0], gcn_vec_constant (<MODE>mode, 0));
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emit_insn (gen_gather<mode>_expr_exec (operands[0], addr, as, v,
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operands[0], exec));
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gcn_gen_undef (<MODE>mode), exec));
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DONE;
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})
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@ -4027,7 +4025,8 @@
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(match_operand:<VnSI> 2 "register_operand")
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(match_operand 3 "immediate_operand")
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(match_operand:SI 4 "gcn_alu_operand")
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(match_operand:DI 5 "")]
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(match_operand:DI 5 "")
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(match_operand:V_MOV 6 "maskload_else_operand")]
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""
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{
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rtx exec = force_reg (DImode, operands[5]);
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@ -4036,18 +4035,18 @@
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operands[2], operands[4],
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INTVAL (operands[3]), exec);
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/* Masked lanes are required to hold zero. */
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emit_move_insn (operands[0], gcn_vec_constant (<MODE>mode, 0));
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if (GET_MODE (addr) == <VnDI>mode)
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emit_insn (gen_gather<mode>_insn_1offset_exec (operands[0], addr,
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const0_rtx, const0_rtx,
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const0_rtx, operands[0],
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exec));
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gcn_gen_undef
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(<MODE>mode),
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operands[0], exec));
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else
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emit_insn (gen_gather<mode>_insn_2offsets_exec (operands[0], operands[1],
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addr, const0_rtx,
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const0_rtx, const0_rtx,
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const0_rtx,
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gcn_gen_undef
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(<MODE>mode),
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operands[0], exec));
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DONE;
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})
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@ -228,3 +228,5 @@
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return gcn_stepped_zero_int_parallel_p (op, 1);
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})
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(define_predicate "maskload_else_operand"
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(match_operand 0 "scratch_operand"))
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