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aarch64: Implement TImode compare-and-swap
This pattern will only be used with the __sync functions, because we do not yet have a bare TImode atomic load. * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Add support for NE comparison of TImode values. (aarch64_emit_load_exclusive): Add support for TImode. (aarch64_emit_store_exclusive): Likewise. (aarch64_split_compare_and_swap): Disable strong_zero_p for TImode. * config/aarch64/atomics.md (@atomic_compare_and_swap<ALLI_TI>): Change iterator from ALLI to ALLI_TI. (@atomic_compare_and_swap<JUST_TI>): New. (@atomic_compare_and_swap<JUST_TI>_lse): New. (aarch64_load_exclusive_pair): New. (aarch64_store_exclusive_pair): New. * config/aarch64/iterators.md (JUST_TI): New. From-SVN: r275965
This commit is contained in:
Richard Henderson
Richard Henderson
parent
e3f15286d1
commit
4a2095ebac
gcc
@ -3,6 +3,19 @@
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* config/aarch64/aarch64.c (aarch64_print_operand): Allow integer
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registers with %R.
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* config/aarch64/aarch64.c (aarch64_gen_compare_reg): Add support
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for NE comparison of TImode values.
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(aarch64_emit_load_exclusive): Add support for TImode.
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(aarch64_emit_store_exclusive): Likewise.
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(aarch64_split_compare_and_swap): Disable strong_zero_p for TImode.
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* config/aarch64/atomics.md (@atomic_compare_and_swap<ALLI_TI>):
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Change iterator from ALLI to ALLI_TI.
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(@atomic_compare_and_swap<JUST_TI>): New.
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(@atomic_compare_and_swap<JUST_TI>_lse): New.
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(aarch64_load_exclusive_pair): New.
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(aarch64_store_exclusive_pair): New.
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* config/aarch64/iterators.md (JUST_TI): New.
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2019-09-19 Feng Xue <fxue@os.amperecomputing.com>
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* ipa-fnsummary.c (set_cond_stmt_execution_predicate): Do not compute
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@ -2039,10 +2039,33 @@ emit_set_insn (rtx x, rtx y)
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rtx
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aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y)
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{
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machine_mode mode = SELECT_CC_MODE (code, x, y);
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rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
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machine_mode cmp_mode = GET_MODE (x);
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machine_mode cc_mode;
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rtx cc_reg;
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emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
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if (cmp_mode == TImode)
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{
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gcc_assert (code == NE);
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cc_mode = CCmode;
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cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM);
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rtx x_lo = operand_subword (x, 0, 0, TImode);
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rtx y_lo = operand_subword (y, 0, 0, TImode);
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emit_set_insn (cc_reg, gen_rtx_COMPARE (cc_mode, x_lo, y_lo));
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rtx x_hi = operand_subword (x, 1, 0, TImode);
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rtx y_hi = operand_subword (y, 1, 0, TImode);
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emit_insn (gen_ccmpdi (cc_reg, cc_reg, x_hi, y_hi,
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gen_rtx_EQ (cc_mode, cc_reg, const0_rtx),
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GEN_INT (AARCH64_EQ)));
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}
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else
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{
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cc_mode = SELECT_CC_MODE (code, x, y);
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cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM);
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emit_set_insn (cc_reg, gen_rtx_COMPARE (cc_mode, x, y));
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}
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return cc_reg;
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}
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@ -2593,7 +2616,6 @@ aarch64_zero_extend_const_eq (machine_mode xmode, rtx x,
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gcc_assert (r != NULL);
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return rtx_equal_p (x, r);
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}
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/* Return TARGET if it is nonnull and a register of mode MODE.
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Otherwise, return a fresh register of mode MODE if we can,
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@ -16814,16 +16836,26 @@ static void
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aarch64_emit_load_exclusive (machine_mode mode, rtx rval,
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rtx mem, rtx model_rtx)
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{
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emit_insn (gen_aarch64_load_exclusive (mode, rval, mem, model_rtx));
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if (mode == TImode)
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emit_insn (gen_aarch64_load_exclusive_pair (gen_lowpart (DImode, rval),
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gen_highpart (DImode, rval),
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mem, model_rtx));
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else
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emit_insn (gen_aarch64_load_exclusive (mode, rval, mem, model_rtx));
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}
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/* Emit store exclusive. */
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static void
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aarch64_emit_store_exclusive (machine_mode mode, rtx bval,
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rtx rval, rtx mem, rtx model_rtx)
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rtx mem, rtx rval, rtx model_rtx)
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{
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emit_insn (gen_aarch64_store_exclusive (mode, bval, rval, mem, model_rtx));
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if (mode == TImode)
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emit_insn (gen_aarch64_store_exclusive_pair
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(bval, mem, operand_subword (rval, 0, 0, TImode),
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operand_subword (rval, 1, 0, TImode), model_rtx));
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else
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emit_insn (gen_aarch64_store_exclusive (mode, bval, mem, rval, model_rtx));
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}
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/* Mark the previous jump instruction as unlikely. */
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@ -16950,7 +16982,7 @@ aarch64_split_compare_and_swap (rtx operands[])
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CBNZ scratch, .label1
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.label2:
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CMP rval, 0. */
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bool strong_zero_p = !is_weak && oldval == const0_rtx;
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bool strong_zero_p = !is_weak && oldval == const0_rtx && mode != TImode;
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label1 = NULL;
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if (!is_weak)
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@ -21,11 +21,11 @@
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;; Instruction patterns.
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(define_expand "@atomic_compare_and_swap<mode>"
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[(match_operand:SI 0 "register_operand") ;; bool out
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(match_operand:ALLI 1 "register_operand") ;; val out
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(match_operand:ALLI 2 "aarch64_sync_memory_operand") ;; memory
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(match_operand:ALLI 3 "nonmemory_operand") ;; expected
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(match_operand:ALLI 4 "aarch64_reg_or_zero") ;; desired
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[(match_operand:SI 0 "register_operand" "") ;; bool out
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(match_operand:ALLI_TI 1 "register_operand" "") ;; val out
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(match_operand:ALLI_TI 2 "aarch64_sync_memory_operand" "") ;; memory
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(match_operand:ALLI_TI 3 "nonmemory_operand" "") ;; expected
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(match_operand:ALLI_TI 4 "aarch64_reg_or_zero" "") ;; desired
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(match_operand:SI 5 "const_int_operand") ;; is_weak
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(match_operand:SI 6 "const_int_operand") ;; mod_s
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(match_operand:SI 7 "const_int_operand")] ;; mod_f
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@ -88,6 +88,30 @@
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}
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)
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(define_insn_and_split "@aarch64_compare_and_swap<mode>"
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[(set (reg:CC CC_REGNUM) ;; bool out
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(unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
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(set (match_operand:JUST_TI 0 "register_operand" "=&r") ;; val out
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(match_operand:JUST_TI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
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(set (match_dup 1)
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(unspec_volatile:JUST_TI
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[(match_operand:JUST_TI 2 "aarch64_reg_or_zero" "rZ") ;; expect
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(match_operand:JUST_TI 3 "aarch64_reg_or_zero" "rZ") ;; desired
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(match_operand:SI 4 "const_int_operand") ;; is_weak
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(match_operand:SI 5 "const_int_operand") ;; mod_s
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(match_operand:SI 6 "const_int_operand")] ;; mod_f
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UNSPECV_ATOMIC_CMPSW))
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(clobber (match_scratch:SI 7 "=&r"))]
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""
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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aarch64_split_compare_and_swap (operands);
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DONE;
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}
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)
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(define_insn "@aarch64_compare_and_swap<mode>_lse"
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[(set (match_operand:SI 0 "register_operand" "+r") ;; val out
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(zero_extend:SI
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@ -133,6 +157,28 @@
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return "casal<atomic_sfx>\t%<w>0, %<w>2, %1";
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})
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(define_insn "@aarch64_compare_and_swap<mode>_lse"
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[(set (match_operand:JUST_TI 0 "register_operand" "+r") ;; val out
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(match_operand:JUST_TI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
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(set (match_dup 1)
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(unspec_volatile:JUST_TI
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[(match_dup 0) ;; expect
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(match_operand:JUST_TI 2 "register_operand" "r") ;; desired
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(match_operand:SI 3 "const_int_operand")] ;; mod_s
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UNSPECV_ATOMIC_CMPSW))]
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"TARGET_LSE"
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{
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enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
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if (is_mm_relaxed (model))
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return "casp\t%0, %R0, %2, %R2, %1";
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else if (is_mm_acquire (model) || is_mm_consume (model))
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return "caspa\t%0, %R0, %2, %R2, %1";
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else if (is_mm_release (model))
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return "caspl\t%0, %R0, %2, %R2, %1";
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else
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return "caspal\t%0, %R0, %2, %R2, %1";
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})
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(define_expand "atomic_exchange<mode>"
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[(match_operand:ALLI 0 "register_operand")
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(match_operand:ALLI 1 "aarch64_sync_memory_operand")
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@ -581,6 +627,24 @@
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}
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)
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(define_insn "aarch64_load_exclusive_pair"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec_volatile:DI
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[(match_operand:TI 2 "aarch64_sync_memory_operand" "Q")
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(match_operand:SI 3 "const_int_operand")]
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UNSPECV_LX))
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(set (match_operand:DI 1 "register_operand" "=r")
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(unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LX))]
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""
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{
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enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
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if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model))
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return "ldxp\t%0, %1, %2";
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else
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return "ldaxp\t%0, %1, %2";
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}
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)
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(define_insn "@aarch64_store_exclusive<mode>"
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[(set (match_operand:SI 0 "register_operand" "=&r")
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(unspec_volatile:SI [(const_int 0)] UNSPECV_SX))
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@ -599,6 +663,25 @@
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}
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)
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(define_insn "aarch64_store_exclusive_pair"
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[(set (match_operand:SI 0 "register_operand" "=&r")
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(unspec_volatile:SI [(const_int 0)] UNSPECV_SX))
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(set (match_operand:TI 1 "aarch64_sync_memory_operand" "=Q")
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(unspec_volatile:TI
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[(match_operand:DI 2 "aarch64_reg_or_zero" "rZ")
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(match_operand:DI 3 "aarch64_reg_or_zero" "rZ")
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(match_operand:SI 4 "const_int_operand")]
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UNSPECV_SX))]
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""
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{
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enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
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if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))
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return "stxp\t%w0, %x2, %x3, %1";
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else
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return "stlxp\t%w0, %x2, %x3, %1";
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}
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)
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(define_expand "mem_thread_fence"
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[(match_operand:SI 0 "const_int_operand")]
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""
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@ -29,6 +29,9 @@
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;; Iterator for HI, SI, DI, some instructions can only work on these modes.
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(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
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;; "Iterator" for just TI -- features like @pattern only work with iterators.
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(define_mode_iterator JUST_TI [TI])
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;; Iterator for QI and HI modes
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(define_mode_iterator SHORT [QI HI])
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