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Fix FMA4 and XOP insns.
2009-12-02 Sebastian Pop <sebastian.pop@amd.com> Richard Henderson <rth@redhat.com> * config/i386/i386-protos.h (ix86_fma4_valid_op_p): Removed. * config/i386/i386.c (ix86_fma4_valid_op_p): Removed. * config/i386/i386.md: Do not use ix86_fma4_valid_op_p. * config/i386/sse.md (fma4_*): Remove alternative with operand 1 matching a memory access. Do not use ix86_fma4_valid_op_p. (xop_*): Same. Do not use ix86_fma4_valid_op_p in FMA4 and XOP splitters. Co-Authored-By: Richard Henderson <rth@redhat.com> From-SVN: r154970
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Sebastian Pop
Sebastian Pop
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@ -1,3 +1,14 @@
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2009-12-02 Sebastian Pop <sebastian.pop@amd.com>
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Richard Henderson <rth@redhat.com>
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* config/i386/i386-protos.h (ix86_fma4_valid_op_p): Removed.
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* config/i386/i386.c (ix86_fma4_valid_op_p): Removed.
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* config/i386/i386.md: Do not use ix86_fma4_valid_op_p.
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* config/i386/sse.md (fma4_*): Remove alternative with operand 1
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matching a memory access. Do not use ix86_fma4_valid_op_p.
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(xop_*): Same.
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Do not use ix86_fma4_valid_op_p in FMA4 and XOP splitters.
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2009-12-02 Richard Henderson <rth@redhat.com>
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* config/i386/i386.c (ix86_fixup_binary_operands): For FMA4, force
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@ -218,8 +218,7 @@ extern void ix86_expand_vector_set (bool, rtx, rtx, int);
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extern void ix86_expand_vector_extract (bool, rtx, rtx, int);
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extern void ix86_expand_reduc_v4sf (rtx (*)(rtx, rtx, rtx), rtx, rtx);
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extern bool ix86_fma4_valid_op_p (rtx [], rtx, int, bool, int, bool);
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extern void ix86_expand_fma4_multiple_memory (rtx [], enum machine_mode);
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extern bool ix86_expand_fma4_multiple_memory (rtx [], enum machine_mode);
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extern void ix86_expand_vec_extract_even_odd (rtx, rtx, rtx, unsigned);
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@ -28807,197 +28807,35 @@ ix86_expand_round (rtx operand0, rtx operand1)
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emit_move_insn (operand0, res);
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}
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/* Validate whether a FMA4 instruction is valid or not.
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OPERANDS is the array of operands.
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NUM is the number of operands.
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USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
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NUM_MEMORY is the maximum number of memory operands to accept.
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NUM_MEMORY less than zero is a special case to allow an operand
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of an instruction to be memory operation.
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when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
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/* Fixup an FMA4 or XOP instruction that has 2 memory input references
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into a form the hardware will allow by using the destination
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register to load one of the memory operations. Presently this is
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used by the multiply/add routines to allow 2 memory references. */
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bool
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ix86_fma4_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
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bool uses_oc0, int num_memory, bool commutative)
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{
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int mem_mask;
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int mem_count;
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int i;
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/* Count the number of memory arguments */
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mem_mask = 0;
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mem_count = 0;
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for (i = 0; i < num; i++)
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{
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enum machine_mode mode = GET_MODE (operands[i]);
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if (register_operand (operands[i], mode))
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;
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else if (memory_operand (operands[i], mode))
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{
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mem_mask |= (1 << i);
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mem_count++;
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}
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else
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{
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rtx pattern = PATTERN (insn);
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/* allow 0 for pcmov */
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if (GET_CODE (pattern) != SET
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|| GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
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|| i < 2
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|| operands[i] != CONST0_RTX (mode))
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return false;
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}
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}
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/* Special case pmacsdq{l,h} where we allow the 3rd argument to be
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a memory operation. */
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if (num_memory < 0)
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{
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num_memory = -num_memory;
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if ((mem_mask & (1 << (num-1))) != 0)
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{
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mem_mask &= ~(1 << (num-1));
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mem_count--;
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}
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}
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/* If there were no memory operations, allow the insn */
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if (mem_mask == 0)
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return true;
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/* Do not allow the destination register to be a memory operand. */
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else if (mem_mask & (1 << 0))
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return false;
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/* If there are too many memory operations, disallow the instruction. While
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the hardware only allows 1 memory reference, before register allocation
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for some insns, we allow two memory operations sometimes in order to allow
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code like the following to be optimized:
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float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
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or similar cases that are vectorized into using the vfmaddss
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instruction. */
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else if (mem_count > num_memory)
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return false;
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/* Don't allow more than one memory operation if not optimizing. */
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else if (mem_count > 1 && !optimize)
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return false;
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else if (num == 4 && mem_count == 1)
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{
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/* formats (destination is the first argument), example vfmaddss:
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xmm1, xmm1, xmm2, xmm3/mem
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xmm1, xmm1, xmm2/mem, xmm3
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xmm1, xmm2, xmm3/mem, xmm1
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xmm1, xmm2/mem, xmm3, xmm1 */
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if (uses_oc0)
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return ((mem_mask == (1 << 1))
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|| (mem_mask == (1 << 2))
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|| (mem_mask == (1 << 3)));
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/* format, example vpmacsdd:
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xmm1, xmm2, xmm3/mem, xmm1 */
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if (commutative)
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return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
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else
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return (mem_mask == (1 << 2));
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}
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else if (num == 4 && num_memory == 2)
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{
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/* If there are two memory operations, we can load one of the memory ops
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into the destination register. This is for optimizing the
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multiply/add ops, which the combiner has optimized both the multiply
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and the add insns to have a memory operation. We have to be careful
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that the destination doesn't overlap with the inputs. */
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rtx op0 = operands[0];
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if (reg_mentioned_p (op0, operands[1])
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|| reg_mentioned_p (op0, operands[2])
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|| reg_mentioned_p (op0, operands[3]))
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return false;
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/* formats (destination is the first argument), example vfmaddss:
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xmm1, xmm1, xmm2, xmm3/mem
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xmm1, xmm1, xmm2/mem, xmm3
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xmm1, xmm2, xmm3/mem, xmm1
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xmm1, xmm2/mem, xmm3, xmm1
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For the oc0 case, we will load either operands[1] or operands[3] into
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operands[0], so any combination of 2 memory operands is ok. */
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if (uses_oc0)
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return true;
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/* format, example vpmacsdd:
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xmm1, xmm2, xmm3/mem, xmm1
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For the integer multiply/add instructions be more restrictive and
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require operands[2] and operands[3] to be the memory operands. */
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if (commutative)
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return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
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else
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return (mem_mask == ((1 << 2) | (1 << 3)));
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}
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else if (num == 3 && num_memory == 1)
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{
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/* formats, example vprotb:
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xmm1, xmm2, xmm3/mem
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xmm1, xmm2/mem, xmm3 */
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if (uses_oc0)
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return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
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/* format, example vpcomeq:
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xmm1, xmm2, xmm3/mem */
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else
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return (mem_mask == (1 << 2));
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}
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else
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gcc_unreachable ();
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return false;
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}
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/* Fixup an FMA4 instruction that has 2 memory input references into a form the
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hardware will allow by using the destination register to load one of the
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memory operations. Presently this is used by the multiply/add routines to
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allow 2 memory references. */
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void
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ix86_expand_fma4_multiple_memory (rtx operands[],
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enum machine_mode mode)
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{
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rtx op0 = operands[0];
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rtx scratch = operands[0];
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if (memory_operand (op0, mode)
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|| reg_mentioned_p (op0, operands[1])
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|| reg_mentioned_p (op0, operands[2])
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|| reg_mentioned_p (op0, operands[3]))
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gcc_unreachable ();
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gcc_assert (register_operand (operands[0], mode));
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gcc_assert (register_operand (operands[1], mode));
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gcc_assert (MEM_P (operands[2]) && MEM_P (operands[3]));
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/* For 2 memory operands, pick either operands[1] or operands[3] to move into
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the destination register. */
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if (memory_operand (operands[1], mode))
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if (reg_mentioned_p (scratch, operands[1]))
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{
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emit_move_insn (op0, operands[1]);
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operands[1] = op0;
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}
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else if (memory_operand (operands[3], mode))
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{
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emit_move_insn (op0, operands[3]);
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operands[3] = op0;
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if (!can_create_pseudo_p ())
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return false;
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scratch = gen_reg_rtx (mode);
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}
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emit_move_insn (scratch, operands[3]);
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if (rtx_equal_p (operands[2], operands[3]))
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operands[2] = operands[3] = scratch;
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else
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gcc_unreachable ();
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return;
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operands[3] = scratch;
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return true;
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}
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/* Table of valid machine attributes. */
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@ -19248,7 +19248,7 @@
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(match_operand:MODEF 1 "register_operand" "x")
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(match_operand:MODEF 2 "register_operand" "x")
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(match_operand:MODEF 3 "register_operand" "x")))]
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"TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)"
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"TARGET_XOP"
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"vpcmov\t{%1, %3, %2, %0|%0, %2, %3, %1}"
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[(set_attr "type" "sse4arg")])
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