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re PR target/42210 (avr: optimizing assignment to a bit field)
PR target/42210
* config/avr/predicates.md (const1_operand, const_0_to_7_operand):
New predicates.
* config/avr/avr.md ("insv"): New insn expander.
("*movbitqi.1-6.a", "*movbitqi.1-6.b", "*movbitqi.0", "*insv.io",
"*insv.not.io", "*insv.reg"): New insns.
Co-Authored-By: Georg-Johann Lay <avr@gjlay.de>
From-SVN: r174685
This commit is contained in:
Richard Henderson
Georg-Johann Lay
parent
efcbfc1c35
commit
48f9d59afe
@ -1,3 +1,13 @@
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2011-06-06 Richard Henderson <rth@redhat.com>
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Georg-Johann Lay <avr@gjlay.de>
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PR target/42210
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* config/avr/predicates.md (const1_operand, const_0_to_7_operand):
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New predicates.
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* config/avr/avr.md ("insv"): New insn expander.
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("*movbitqi.1-6.a", "*movbitqi.1-6.b", "*movbitqi.0", "*insv.io",
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"*insv.not.io", "*insv.reg"): New insns.
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2011-06-06 Hans-Peter Nilsson <hp@bitrange.com>
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PR target/49285
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@ -3389,6 +3389,119 @@
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[(set_attr "length" "3")
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(set_attr "cc" "clobber")])
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;; Some combiner patterns dealing with bits.
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;; See PR42210
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;; Move bit $3.0 into bit $0.$4
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(define_insn "*movbitqi.1-6.a"
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[(set (match_operand:QI 0 "register_operand" "=r")
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(ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
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(match_operand:QI 2 "single_zero_operand" "n"))
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(and:QI (ashift:QI (match_operand:QI 3 "register_operand" "r")
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(match_operand:QI 4 "const_0_to_7_operand" "n"))
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(match_operand:QI 5 "single_one_operand" "n"))))]
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"INTVAL(operands[4]) == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))
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&& INTVAL(operands[4]) == exact_log2 (INTVAL(operands[5]) & GET_MODE_MASK (QImode))"
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"bst %3,0\;bld %0,%4"
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[(set_attr "length" "2")
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(set_attr "cc" "none")])
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;; Move bit $3.0 into bit $0.$4
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;; Variation of above. Unfortunately, there is no canonicalized representation
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;; of moving around bits. So what we see here depends on how user writes down
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;; bit manipulations.
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(define_insn "*movbitqi.1-6.b"
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[(set (match_operand:QI 0 "register_operand" "=r")
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(ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
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(match_operand:QI 2 "single_zero_operand" "n"))
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(ashift:QI (and:QI (match_operand:QI 3 "register_operand" "r")
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(const_int 1))
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(match_operand:QI 4 "const_0_to_7_operand" "n"))))]
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"INTVAL(operands[4]) == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
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"bst %3,0\;bld %0,%4"
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[(set_attr "length" "2")
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(set_attr "cc" "none")])
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;; Move bit $3.0 into bit $0.0.
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;; For bit 0, combiner generates slightly different pattern.
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(define_insn "*movbitqi.0"
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[(set (match_operand:QI 0 "register_operand" "=r")
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(ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
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(match_operand:QI 2 "single_zero_operand" "n"))
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(and:QI (match_operand:QI 3 "register_operand" "r")
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(const_int 1))))]
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"0 == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
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"bst %3,0\;bld %0,0"
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[(set_attr "length" "2")
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(set_attr "cc" "none")])
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;; Move bit $2.0 into bit $0.7.
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;; For bit 7, combiner generates slightly different pattern
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(define_insn "*movbitqi.7"
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[(set (match_operand:QI 0 "register_operand" "=r")
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(ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
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(const_int 127))
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(ashift:QI (match_operand:QI 2 "register_operand" "r")
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(const_int 7))))]
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""
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"bst %2,0\;bld %0,7"
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[(set_attr "length" "2")
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(set_attr "cc" "none")])
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;; Combiner transforms above four pattern into ZERO_EXTRACT if it sees MEM
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;; and input/output match. We provide a special pattern for this, because
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;; in contrast to a IN/BST/BLD/OUT sequence we need less registers and the
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;; operation on I/O is atomic.
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(define_insn "*insv.io"
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[(set (zero_extract:QI (mem:QI (match_operand 0 "low_io_address_operand" "n,n,n"))
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(const_int 1)
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(match_operand:QI 1 "const_0_to_7_operand" "n,n,n"))
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(match_operand:QI 2 "nonmemory_operand" "L,P,r"))]
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""
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"@
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cbi %m0-0x20,%1
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sbi %m0-0x20,%1
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sbrc %2,0\;sbi %m0-0x20,%1\;sbrs %2,0\;cbi %m0-0x20,%1"
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[(set_attr "length" "1,1,4")
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(set_attr "cc" "none")])
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(define_insn "*insv.not.io"
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[(set (zero_extract:QI (mem:QI (match_operand 0 "low_io_address_operand" "n"))
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(const_int 1)
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(match_operand:QI 1 "const_0_to_7_operand" "n"))
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(not:QI (match_operand:QI 2 "register_operand" "r")))]
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""
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"sbrs %2,0\;sbi %m0-0x20,%1\;sbrc %2,0\;cbi %m0-0x20,%1"
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[(set_attr "length" "4")
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(set_attr "cc" "none")])
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;; The insv expander.
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;; We only support 1-bit inserts
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(define_expand "insv"
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[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "")
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(match_operand:QI 1 "const1_operand" "") ; width
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(match_operand:QI 2 "const_0_to_7_operand" "")) ; pos
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(match_operand:QI 3 "nonmemory_operand" ""))]
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"optimize"
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"")
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;; Insert bit $2.0 into $0.$1
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(define_insn "*insv.reg"
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[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r,d,d,l,l")
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(const_int 1)
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(match_operand:QI 1 "const_0_to_7_operand" "n,n,n,n,n"))
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(match_operand:QI 2 "nonmemory_operand" "r,L,P,L,P"))]
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""
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"@
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bst %2,0\;bld %0,%1
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andi %0,lo8(~(1<<%1))
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ori %0,lo8(1<<%1)
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clt\;bld %0,%1
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set\;bld %0,%1"
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[(set_attr "length" "2,1,1,2,2")
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(set_attr "cc" "none,set_zn,set_zn,none,none")])
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;; Some combine patterns that try to fix bad code when a value is composed
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;; from byte parts like in PR27663.
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@ -62,6 +62,17 @@
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(and (match_code "const_int,const_double")
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(match_test "op == CONST0_RTX (mode)")))
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;; Return 1 if OP is the one constant integer for MODE.
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(define_predicate "const1_operand"
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(and (match_code "const_int")
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(match_test "op == CONST1_RTX (mode)")))
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;; Return 1 if OP is constant integer 0..7 for MODE.
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(define_predicate "const_0_to_7_operand"
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(and (match_code "const_int")
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(match_test "IN_RANGE (INTVAL (op), 0, 7)")))
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;; Returns true if OP is either the constant zero or a register.
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(define_predicate "reg_or_0_operand"
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(ior (match_operand 0 "register_operand")
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