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ia64.h (HARD_REGNO_NREGS): Handle RFmode.

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* config/ia64/ia64.h (HARD_REGNO_NREGS): Handle RFmode.
	(HARD_REGNO_MODE_OK): Ditto.
	(MODES_TIEABLE_P): Ditto.
	(HARD_REGNO_CALLER_SAVE_MODE): Ditto.
	(CLASS_MAX_NREGS): Ditto.
	* config/ia64/ia64.c (ia64_print_operand_address): Add R format.
	* config/ia64/ia64.md (divsf3_internal_thr): Removed.
	(divdf3_internal_thr): Removed.
	* config/ia64/div.md: New file.
	* config/ia64/constraints.md: Add H constraint.

From-SVN: r126930
This commit is contained in:
Steve Ellcey 2007-07-25 20:09:07 +00:00 committed by Steve Ellcey
parent be5b01f393
commit 4883241c18
6 changed files with 351 additions and 124 deletions
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13
gcc/ChangeLog
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@ -1,3 +1,16 @@
2007-07-25 Steve Ellcey <sje@cup.hp.com>
* config/ia64/ia64.h (HARD_REGNO_NREGS): Handle RFmode.
(HARD_REGNO_MODE_OK): Ditto.
(MODES_TIEABLE_P): Ditto.
(HARD_REGNO_CALLER_SAVE_MODE): Ditto.
(CLASS_MAX_NREGS): Ditto.
* config/ia64/ia64.c (ia64_print_operand_address): Add R format.
* config/ia64/ia64.md (divsf3_internal_thr): Removed.
(divdf3_internal_thr): Removed.
* config/ia64/div.md: New file.
* config/ia64/constraints.md: Add H constraint.
2007-07-25 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* sbitmap.c (sbitmap_verify_popcount, sbitmap_alloc_with_popcount,

5
gcc/config/ia64/constraints.md
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@ -90,6 +90,11 @@
(and (match_code "const_double")
(match_test "op == CONST0_RTX (mode) || op == CONST1_RTX (mode)")))
(define_constraint "H"
"0.0"
(and (match_code "const_double")
(match_test "op == CONST0_RTX (mode)")))
;; Extra constraints
;; Note that while this accepts mem, it only accepts non-volatile mem,

313
gcc/config/ia64/div.md Normal file
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@ -0,0 +1,313 @@
;; For the internal conditional math routines:
;; operand 0 is always the result
;; operand 1 is always the predicate
;; operand 2, 3, and sometimes 4 are the input values.
;; operand 4 or 5 is the floating point status register to use.
;; operand 5 or 6 is the rounding to do. (0 = single, 1 = double, 2 = none)
;;
;; addrf3_cond - F0 = F2 + F3
;; subrf3_cond - F0 = F2 - F3
;; mulrf3_cond - F0 = F2 * F3
;; nmulrf3_cond - F0 = - (F2 * F3)
;; m1addrf4_cond - F0 = (F2 * F3) + F4
;; m1subrf4_cond - F0 = (F2 * F3) - F4
;; m2addrf4_cond - F0 = F2 + (F3 * F4)
;; m2subrf4_cond - F0 = F2 - (F3 * F4)
;; Basic plus/minus/mult operations
(define_insn "addrf3_cond"
[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
(const_int 0))
(plus:RF
(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
(match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
(match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
(use (match_operand:SI 5 "const_int_operand" ""))
(use (match_operand:SI 6 "const_int_operand" ""))]
""
"(%1) fadd%R6.s%5 %0 = %F2, %F3"
[(set_attr "itanium_class" "fmac")
(set_attr "predicable" "no")])
(define_insn "subrf3_cond"
[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
(const_int 0))
(minus:RF
(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
(match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
(match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
(use (match_operand:SI 5 "const_int_operand" ""))
(use (match_operand:SI 6 "const_int_operand" ""))]
""
"(%1) fsub%R6.s%5 %0 = %F2, %F3"
[(set_attr "itanium_class" "fmac")
(set_attr "predicable" "no")])
(define_insn "mulrf3_cond"
[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
(const_int 0))
(mult:RF
(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
(match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
(match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
(use (match_operand:SI 5 "const_int_operand" ""))
(use (match_operand:SI 6 "const_int_operand" ""))]
""
"(%1) fmpy%R6.s%5 %0 = %F2, %F3"
[(set_attr "itanium_class" "fmac")
(set_attr "predicable" "no")])
;; neg-mult operation
(define_insn "nmulrf3_cond"
[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
(const_int 0))
(neg:RF (mult:RF
(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
(match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")))
(match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
(use (match_operand:SI 5 "const_int_operand" ""))
(use (match_operand:SI 6 "const_int_operand" ""))]
""
"(%1) fnmpy%R6.s%5 %0 = %F2, %F3"
[(set_attr "itanium_class" "fmac")
(set_attr "predicable" "no")])
;; add-mult/sub-mult operations (mult as op1)
(define_insn "m1addrf4_cond"
[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
(const_int 0))
(plus:RF
(mult:RF
(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
(match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
(match_operand:RF 4 "fr_reg_or_fp01_operand" "fG,fG"))
(match_operand:RF 5 "fr_reg_or_0_operand" "0,H")))
(use (match_operand:SI 6 "const_int_operand" ""))
(use (match_operand:SI 7 "const_int_operand" ""))]
""
"(%1) fma%R7.s%6 %0 = %F2, %F3, %F4"
[(set_attr "itanium_class" "fmac")
(set_attr "predicable" "no")])
(define_insn "m1subrf4_cond"
[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
(const_int 0))
(minus:RF
(mult:RF
(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
(match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
(match_operand:RF 4 "fr_reg_or_fp01_operand" "fG,fG"))
(match_operand:RF 5 "fr_reg_or_0_operand" "0,H")))
(use (match_operand:SI 6 "const_int_operand" ""))
(use (match_operand:SI 7 "const_int_operand" ""))]
""
"(%1) fms%R7.s%6 %0 = %F2, %F3, %F4"
[(set_attr "itanium_class" "fmac")
(set_attr "predicable" "no")])
;; add-mult/sub-mult operations (mult as op2)
(define_insn "m2addrf4_cond"
[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
(const_int 0))
(plus:RF
(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
(mult:RF
(match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")
(match_operand:RF 4 "fr_reg_or_fp01_operand" "fG,fG")))
(match_operand:RF 5 "fr_reg_or_0_operand" "0,H")))
(use (match_operand:SI 6 "const_int_operand" ""))
(use (match_operand:SI 7 "const_int_operand" ""))]
""
"(%1) fma%R7.s%6 %0 = %F3, %F4, %F2"
[(set_attr "itanium_class" "fmac")
(set_attr "predicable" "no")])
(define_insn "m2subrf4_cond"
[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
(const_int 0))
(minus:RF
(match_operand:RF 2 "fr_reg_or_fp01_operand" "fg,fG")
(mult:RF
(match_operand:RF 3 "fr_reg_or_fp01_operand" "fg,fG")
(match_operand:RF 4 "fr_reg_or_fp01_operand" "fg,fG")))
(match_operand:RF 5 "fr_reg_or_0_operand" "0,H")))
(use (match_operand:SI 6 "const_int_operand" ""))
(use (match_operand:SI 7 "const_int_operand" ""))]
""
"(%1) fnma%R7.s%6 %0 = %F3, %F4, %F2"
[(set_attr "itanium_class" "fmac")
(set_attr "predicable" "no")])
;; Conversions to/from RF and SF/DF/XF
;; These conversions should not generate any code but make it possible
;; for all the instructions used to implement floating point division
;; to be written for RFmode only and to not have to handle multiple
;; modes or to have to handle a register in more than one mode.
(define_mode_macro SDX_F [SF DF XF])
(define_insn "extend<mode>rf2"
[(set (match_operand:RF 0 "fr_register_operand" "=f")
(float_extend:RF (match_operand:SDX_F 1 "fr_register_operand" "f")))]
""
"#"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "yes")])
(define_split
[(set (match_operand:RF 0 "fr_register_operand" "")
(float_extend:RF (match_operand:SDX_F 1 "fr_register_operand" "")))]
"reload_completed"
[(set (match_dup 0) (match_dup 2))]
{
operands[2] = gen_rtx_REG (RFmode, REGNO (operands[1]));
})
(define_insn "truncrf<mode>2"
[(set (match_operand:SDX_F 0 "fr_register_operand" "=f")
(float_truncate:SDX_F (match_operand:RF 1 "fr_register_operand" "f")))]
""
"#"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "yes")])
(define_split
[(set (match_operand:SDX_F 0 "fr_register_operand" "")
(float_truncate:SDX_F (match_operand:RF 1 "fr_register_operand" "")))]
"reload_completed"
[(set (match_dup 0) (match_dup 2))]
{
operands[2] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
})
;; Reciprical approximation
(define_insn "recip_approx_rf"
[(set (match_operand:RF 0 "fr_register_operand" "=f")
(div:RF (match_operand:RF 1 "fr_register_operand" "f")
(match_operand:RF 2 "fr_register_operand" "f")))
(set (match_operand:BI 3 "register_operand" "=c")
(unspec:BI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX))
(use (match_operand:SI 4 "const_int_operand" ""))]
""
"frcpa.s%4 %0, %3 = %1, %2"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
;; Single precision floating point division (maximum throughput algorithm).
(define_expand "divsf3_internal_thr"
[(set (match_operand:SF 0 "fr_register_operand" "")
(div:SF (match_operand:SF 1 "fr_register_operand" "")
(match_operand:SF 2 "fr_register_operand" "")))]
"TARGET_INLINE_FLOAT_DIV"
{
rtx y = gen_reg_rtx (RFmode);
rtx a = gen_reg_rtx (RFmode);
rtx b = gen_reg_rtx (RFmode);
rtx e = gen_reg_rtx (RFmode);
rtx y1 = gen_reg_rtx (RFmode);
rtx y2 = gen_reg_rtx (RFmode);
rtx q = gen_reg_rtx (RFmode);
rtx r = gen_reg_rtx (RFmode);
rtx q_res = gen_reg_rtx (RFmode);
rtx cond = gen_reg_rtx (BImode);
rtx zero = CONST0_RTX (RFmode);
rtx one = CONST1_RTX (RFmode);
rtx status0 = CONST0_RTX (SImode);
rtx status1 = CONST1_RTX (SImode);
rtx trunc_sgl = CONST0_RTX (SImode);
rtx trunc_off = CONST2_RTX (SImode);
/* Empty conversions to put inputs into RFmode. */
emit_insn (gen_extendsfrf2 (a, operands[1]));
emit_insn (gen_extendsfrf2 (b, operands[2]));
/* y = 1 / b */
emit_insn (gen_recip_approx_rf (y, a, b, cond, status0));
/* e = 1 - (b * y) */
emit_insn (gen_m2subrf4_cond (e, cond, one, b, y, zero, status1, trunc_off));
/* y1 = y + (y * e) */
emit_insn (gen_m2addrf4_cond (y1, cond, y, y, e, zero, status1, trunc_off));
/* y2 = y + (y1 * e) */
emit_insn (gen_m2addrf4_cond (y2, cond, y, y1, e, zero, status1, trunc_off));
/* q = single(a * y2) */
emit_insn (gen_mulrf3_cond (q, cond, a, y2, zero, status1, trunc_sgl));
/* r = a - (q * b) */
emit_insn (gen_m2subrf4_cond (r, cond, a, q, b, zero, status1, trunc_off));
/* Q = single (q + (r * y2)) */
emit_insn (gen_m2addrf4_cond (q_res, cond, q, r, y2, y, status0, trunc_sgl));
/* Conversion back into SFmode. */
emit_insn (gen_truncrfsf2 (operands[0], q_res));
DONE;
})
;; Double precision floating point division (maximum throughput algorithm).
(define_expand "divdf3_internal_thr"
[(set (match_operand:DF 0 "fr_register_operand" "")
(div:DF (match_operand:DF 1 "fr_register_operand" "")
(match_operand:DF 2 "fr_register_operand" "")))]
"TARGET_INLINE_FLOAT_DIV"
{
rtx q_res = gen_reg_rtx (RFmode);
rtx a = gen_reg_rtx (RFmode);
rtx b = gen_reg_rtx (RFmode);
rtx y = gen_reg_rtx (RFmode);
rtx e = gen_reg_rtx (RFmode);
rtx y1 = gen_reg_rtx (RFmode);
rtx e1 = gen_reg_rtx (RFmode);
rtx y2 = gen_reg_rtx (RFmode);
rtx e2 = gen_reg_rtx (RFmode);
rtx y3 = gen_reg_rtx (RFmode);
rtx q = gen_reg_rtx (RFmode);
rtx r = gen_reg_rtx (RFmode);
rtx cond = gen_reg_rtx (BImode);
rtx zero = CONST0_RTX (RFmode);
rtx one = CONST1_RTX (RFmode);
rtx status0 = CONST0_RTX (SImode);
rtx status1 = CONST1_RTX (SImode);
rtx trunc_dbl = CONST1_RTX (SImode);
rtx trunc_off = CONST2_RTX (SImode);
/* Empty conversions to put inputs into RFmode */
emit_insn (gen_extenddfrf2 (a, operands[1]));
emit_insn (gen_extenddfrf2 (b, operands[2]));
/* y = 1 / b */
emit_insn (gen_recip_approx_rf (y, a, b, cond, status0));
/* e = 1 - (b * y) */
emit_insn (gen_m2subrf4_cond (e, cond, one, b, y, zero, status1, trunc_off));
/* y1 = y + (y * e) */
emit_insn (gen_m2addrf4_cond (y1, cond, y, y, e, zero, status1, trunc_off));
/* e1 = e * e */
emit_insn (gen_mulrf3_cond (e1, cond, e, e, zero, status1, trunc_off));
/* y2 = y1 + (y1 * e1) */
emit_insn (gen_m2addrf4_cond (y2, cond, y1, y1, e1, zero, status1, trunc_off));
/* e2 = e1 * e1 */
emit_insn (gen_mulrf3_cond (e2, cond, e1, e1, zero, status1, trunc_off));
/* y3 = y2 + (y2 * e2) */
emit_insn (gen_m2addrf4_cond (y3, cond, y2, y2, e2, zero, status1, trunc_off));
/* q = double (a * y3) */
emit_insn (gen_mulrf3_cond (q, cond, a, y3, zero, status1, trunc_dbl));
/* r = a - (b * q) */
emit_insn (gen_m2subrf4_cond (r, cond, a, b, q, zero, status1, trunc_off));
/* Q = double (q + (r * y3)) */
emit_insn (gen_m2addrf4_cond (q_res, cond, q, r, y3, y, status0, trunc_dbl));
/* Conversion back into DFmode */
emit_insn (gen_truncrfdf2 (operands[0], q_res));
DONE;
})

12
gcc/config/ia64/ia64.c
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@ -4496,6 +4496,7 @@ ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
O Append .acq for volatile load.
P Postincrement of a MEM.
Q Append .rel for volatile store.
R Print .s .d or nothing for a single, double or no truncation.
S Shift amount for shladd instruction.
T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
for Intel assembler.
@ -4636,6 +4637,17 @@ ia64_print_operand (FILE * file, rtx x, int code)
fputs(".rel", file);
return;
case 'R':
if (x == CONST0_RTX (GET_MODE (x)))
fputs(".s", file);
else if (x == CONST1_RTX (GET_MODE (x)))
fputs(".d", file);
else if (x == CONST2_RTX (GET_MODE (x)))
;
else
output_operand_lossage ("invalid %%R value");
return;
case 'S':
fprintf (file, "%d", exact_log2 (INTVAL (x)));
return;

10
gcc/config/ia64/ia64.h
View File

@ -645,6 +645,7 @@ while (0)
: PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
: PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
: FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \
: FR_REGNO_P (REGNO) && (MODE) == RFmode ? 1 \
: FR_REGNO_P (REGNO) && (MODE) == XCmode ? 2 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
@ -660,7 +661,7 @@ while (0)
: PR_REGNO_P (REGNO) ? \
(MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
: GR_REGNO_P (REGNO) ? \
(MODE) != CCImode && (MODE) != XFmode && (MODE) != XCmode \
(MODE) != CCImode && (MODE) != XFmode && (MODE) != XCmode && (MODE) != RFmode \
: AR_REGNO_P (REGNO) ? (MODE) == DImode \
: BR_REGNO_P (REGNO) ? (MODE) == DImode \
: 0)
@ -677,15 +678,15 @@ while (0)
we can't tie it with any other modes. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
&& ((((MODE1) == XFmode) || ((MODE1) == XCmode)) \
== (((MODE2) == XFmode) || ((MODE2) == XCmode))) \
&& ((((MODE1) == XFmode) || ((MODE1) == XCmode) || ((MODE1) == RFmode)) \
== (((MODE2) == XFmode) || ((MODE2) == XCmode) || ((MODE1) == RFmode))) \
&& (((MODE1) == BImode) == ((MODE2) == BImode)))
/* Specify the modes required to caller save a given hard regno.
We need to ensure floating pt regs are not saved as DImode. */
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
((FR_REGNO_P (REGNO) && (NREGS) == 1) ? XFmode \
((FR_REGNO_P (REGNO) && (NREGS) == 1) ? RFmode \
: choose_hard_reg_mode ((REGNO), (NREGS), false))
/* Handling Leaf Functions */
@ -883,6 +884,7 @@ enum reg_class
#define CLASS_MAX_NREGS(CLASS, MODE) \
((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
: (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XFmode) ? 1 \
: (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == RFmode) ? 1 \
: (((CLASS) == FR_REGS || (CLASS) == FP_REGS) && (MODE) == XCmode) ? 2 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

122
gcc/config/ia64/ia64.md
View File

@ -3109,60 +3109,6 @@
}
[(set_attr "predicable" "no")])
(define_insn_and_split "divsf3_internal_thr"
[(set (match_operand:SF 0 "fr_register_operand" "=&f")
(div:SF (match_operand:SF 1 "fr_register_operand" "f")
(match_operand:SF 2 "fr_register_operand" "f")))
(clobber (match_scratch:XF 3 "=&f"))
(clobber (match_scratch:XF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
"TARGET_INLINE_FLOAT_DIV == INL_MAX_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 0))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 10)
(mult:XF (match_dup 8) (match_dup 6))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(plus:XF (mult:XF (match_dup 3) (match_dup 3))
(match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 6)
(plus:XF (mult:XF (match_dup 3) (match_dup 6))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 9)
(float_truncate:SF
(mult:XF (match_dup 7) (match_dup 6))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 4)
(minus:XF (match_dup 7)
(mult:XF (match_dup 8) (match_dup 3))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(set (match_dup 0)
(float_truncate:SF
(plus:XF (mult:XF (match_dup 4) (match_dup 6))
(match_dup 3)))))
]
{
operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
operands[10] = CONST1_RTX (XFmode);
}
[(set_attr "predicable" "no")])
;; Inline square root.
(define_insn "*sqrt_approx"
@ -3615,72 +3561,6 @@
}
[(set_attr "predicable" "no")])
(define_insn_and_split "divdf3_internal_thr"
[(set (match_operand:DF 0 "fr_register_operand" "=&f")
(div:DF (match_operand:DF 1 "fr_register_operand" "f")
(match_operand:DF 2 "fr_register_operand" "f")))
(clobber (match_scratch:XF 3 "=&f"))
(clobber (match_scratch:DF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
"TARGET_INLINE_FLOAT_DIV == INL_MAX_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 0))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 10)
(mult:XF (match_dup 8) (match_dup 6))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 6)
(plus:XF (mult:XF (match_dup 3) (match_dup 6))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(mult:XF (match_dup 3) (match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 6)
(plus:XF (mult:XF (match_dup 3) (match_dup 6))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(mult:XF (match_dup 3) (match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 6)
(plus:XF (mult:XF (match_dup 3) (match_dup 6))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 9)
(float_truncate:DF
(mult:XF (match_dup 7) (match_dup 6))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 4)
(minus:DF (match_dup 1)
(mult:DF (match_dup 2) (match_dup 9))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(set (match_dup 0)
(plus:DF (mult:DF (match_dup 4) (match_dup 0))
(match_dup 9))))
]
{
operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
operands[10] = CONST1_RTX (XFmode);
}
[(set_attr "predicable" "no")])
;; Inline square root.
(define_expand "sqrtdf2"
@ -6541,3 +6421,5 @@
(include "vect.md")
;; Atomic operations
(include "sync.md")
;; New division operations
(include "div.md")