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re PR other/8062 (double precision loads and stores missing from xmmintrin.h)
* mmintrin.h: Guard by __MMX__ * xmmintrin.h: Guard by __SSE__ PR other/8062 * xmmintrin.h (_MM_SHUFFLE2): New macro. (_mm_load*_?d): New functions. (_mm_set*_?d): New functions. (_mm_store*_?d): New functions. From-SVN: r58252
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Jan Hubicka
Jan Hubicka
parent
d768a5895b
commit
48126a9798
@ -1,3 +1,14 @@
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Thu Oct 17 18:40:47 CEST 2002 Jan Hubicka <jh@suse.cz>
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* mmintrin.h: Guard by __MMX__
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* xmmintrin.h: Guard by __SSE__
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PR other/8062
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* xmmintrin.h (_MM_SHUFFLE2): New macro.
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(_mm_load*_?d): New functions.
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(_mm_set*_?d): New functions.
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(_mm_store*_?d): New functions.
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Wed Oct 16 15:01:29 CEST 2002 Jan Hubicka <jh@suse.cz>
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Really commit patch announced at Oct 14
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@ -13315,6 +13315,11 @@ ix86_expand_builtin (exp, target, subtarget, mode, ignore)
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case IX86_BUILTIN_STORERPD:
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return ix86_expand_store_builtin (CODE_FOR_sse2_movapd, arglist);
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case IX86_BUILTIN_CLRPD:
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target = gen_reg_rtx (V2DFmode);
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emit_insn (gen_sse_clrv2df (target));
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return target;
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case IX86_BUILTIN_MFENCE:
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emit_insn (gen_sse2_mfence ());
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return 0;
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@ -18810,6 +18810,17 @@
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(set_attr "memory" "none")
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(set_attr "mode" "V4SF")])
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;; Use xor, but don't show input operands so they aren't live before
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;; this insn.
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(define_insn "sse_clrv2df"
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[(set (match_operand:V2DF 0 "register_operand" "=x")
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(unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
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"TARGET_SSE2"
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"xorpd\t{%0, %0|%0, %0}"
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[(set_attr "type" "sselog")
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(set_attr "memory" "none")
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(set_attr "mode" "V4SF")])
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;; SSE mask-generating compares
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(define_insn "maskcmpv4sf3"
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@ -30,6 +30,9 @@
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#ifndef _MMINTRIN_H_INCLUDED
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#define _MMINTRIN_H_INCLUDED
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#ifndef __MMX__
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# error "MMX instruction set not enabled"
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#else
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/* The data type intended for user use. */
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typedef unsigned long long __m64 __attribute__ ((__aligned__ (8)));
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@ -539,4 +542,5 @@ _mm_set1_pi8 (char __b)
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return _mm_set1_pi32 (__i);
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}
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#endif /* __MMX__ */
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#endif /* _MMINTRIN_H_INCLUDED */
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@ -30,6 +30,10 @@
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#ifndef _XMMINTRIN_H_INCLUDED
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#define _XMMINTRIN_H_INCLUDED
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#ifndef __SSE__
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# error "SSE instruction set not enabled"
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#else
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/* We need type definitions from the MMX header file. */
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#include <mmintrin.h>
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@ -1082,9 +1086,159 @@ typedef int __v4si __attribute__ ((mode (V4SI)));
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typedef int __v8hi __attribute__ ((mode (V8HI)));
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typedef int __v16qi __attribute__ ((mode (V16QI)));
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/* Create a selector for use with the SHUFPD instruction. */
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#define _MM_SHUFFLE2(fp1,fp0) \
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(((fp1) << 1) | (fp0))
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#define __m128i __v2di
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#define __m128d __v2df
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/* Create a vector with element 0 as *P and the rest zero. */
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static __inline __m128d
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_mm_load_sd (double *__P)
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{
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return (__m128d) __builtin_ia32_loadsd (__P);
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}
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/* Create a vector with all two elements equal to *P. */
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static __inline __m128d
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_mm_load1_pd (double *__P)
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{
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__v2df __tmp = __builtin_ia32_loadsd (__P);
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return (__m128d) __builtin_ia32_shufpd (__tmp, __tmp, _MM_SHUFFLE2 (0,0));
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}
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static __inline __m128d
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_mm_load_pd1 (double *__P)
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{
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return _mm_load1_pd (__P);
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}
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/* Load two DPFP values from P. The addresd must be 16-byte aligned. */
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static __inline __m128d
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_mm_load_pd (double *__P)
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{
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return (__m128d) __builtin_ia32_loadapd (__P);
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}
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/* Load two DPFP values from P. The addresd need not be 16-byte aligned. */
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static __inline __m128d
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_mm_loadu_pd (double *__P)
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{
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return (__m128d) __builtin_ia32_loadupd (__P);
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}
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/* Load two DPFP values in reverse order. The addresd must be aligned. */
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static __inline __m128d
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_mm_loadr_pd (double *__P)
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{
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__v2df __tmp = __builtin_ia32_loadapd (__P);
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return (__m128d) __builtin_ia32_shufpd (__tmp, __tmp, _MM_SHUFFLE2 (0,1));
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}
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/* Create a vector with element 0 as F and the rest zero. */
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static __inline __m128d
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_mm_set_sd (double __F)
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{
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return (__m128d) __builtin_ia32_loadsd (&__F);
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}
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/* Create a vector with all two elements equal to F. */
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static __inline __m128d
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_mm_set1_pd (double __F)
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{
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__v2df __tmp = __builtin_ia32_loadsd (&__F);
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return (__m128d) __builtin_ia32_shufpd (__tmp, __tmp, _MM_SHUFFLE2 (0,0));
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}
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static __inline __m128d
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_mm_set_pd1 (double __F)
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{
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return _mm_set1_pd (__F);
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}
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/* Create the vector [Z Y]. */
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static __inline __m128d
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_mm_set_pd (double __Z, double __Y)
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{
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union {
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double __a[2];
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__m128d __v;
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} __u;
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__u.__a[0] = __Y;
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__u.__a[1] = __Z;
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return __u.__v;
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}
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/* Create the vector [Y Z]. */
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static __inline __m128d
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_mm_setr_pd (double __Z, double __Y)
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{
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return _mm_set_pd (__Y, __Z);
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}
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/* Create a vector of zeros. */
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static __inline __m128d
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_mm_setzero_pd (void)
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{
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return (__m128d) __builtin_ia32_setzeropd ();
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}
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/* Stores the lower DPFP value. */
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static __inline void
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_mm_store_sd (double *__P, __m128d __A)
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{
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__builtin_ia32_storesd (__P, (__v2df)__A);
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}
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/* Store the lower DPFP value acrosd two words. */
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static __inline void
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_mm_store1_pd (double *__P, __m128d __A)
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{
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__v2df __va = (__v2df)__A;
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__v2df __tmp = __builtin_ia32_shufpd (__va, __va, _MM_SHUFFLE2 (0,0));
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__builtin_ia32_storeapd (__P, __tmp);
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}
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static __inline void
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_mm_store_pd1 (double *__P, __m128d __A)
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{
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_mm_store1_pd (__P, __A);
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}
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/* Store two DPFP values. The addresd must be 16-byte aligned. */
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static __inline void
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_mm_store_pd (double *__P, __m128d __A)
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{
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__builtin_ia32_storeapd (__P, (__v2df)__A);
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}
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/* Store two DPFP values. The addresd need not be 16-byte aligned. */
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static __inline void
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_mm_storeu_pd (double *__P, __m128d __A)
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{
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__builtin_ia32_storeupd (__P, (__v2df)__A);
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}
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/* Store two DPFP values in reverse order. The addresd must be aligned. */
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static __inline void
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_mm_storer_pd (double *__P, __m128d __A)
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{
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__v2df __va = (__v2df)__A;
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__v2df __tmp = __builtin_ia32_shufpd (__va, __va, _MM_SHUFFLE2 (0,1));
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__builtin_ia32_storeapd (__P, __tmp);
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}
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/* Sets the low DPFP value of A from the low value of B. */
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static __inline __m128d
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_mm_move_sd (__m128d __A, __m128d __B)
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{
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return (__m128d) __builtin_ia32_movsd ((__v2df)__A, (__v2df)__B);
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}
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static __inline __m128d
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_mm_add_pd (__m128d __A, __m128d __B)
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{
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@ -2013,6 +2167,7 @@ _mm_mfence (void)
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__builtin_ia32_mfence ();
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}
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#endif /* __SSE2_BUILTINS__ */
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#endif /* __SSE2__ */
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#endif /* __SSE__ */
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#endif /* _XMMINTRIN_H_INCLUDED */
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