From 47f67e51560a5cb55fa2720bcb56d0d29a53ca85 Mon Sep 17 00:00:00 2001 From: Peter Bergner Date: Sat, 10 Oct 2009 13:43:31 -0500 Subject: [PATCH] configure.ac: Add test for dci instruction. * configure.ac: Add test for dci instruction. * configure: Regenerate. * config.in: Likewise. * config.gcc: Handle --with-cpu=476 and --with-cpu=476fp. * doc/invoke.texi: Add cpu_type 476 and 476fp. (-mmulhw): Add 476 to description. (-mdlmzb): Likewise. * config/rs6000/t-fprules (MULTILIB_MATCHES_FLOAT): Include -mcpu=476. * config/rs6000/rs6000.c (processor_costs): Add ppc476_cost. (processor_target_table): Add 476 and 476fp entries. (rs6000_override_options): Use ppc476_cost for PROCESSOR_PPC476. (rs6000_issue_rate): Add CPU_PPC476. * config/rs6000/rs6000.h (ASM_CPU_476_SPEC): Define. (ASM_CPU_SPEC): Pass %(asm_cpu_476) for -mcpu=476 and -mcpu=476fp. (processor_type): Add PROCESSOR_PPC476. (EXTRA_SPECS): Add asm_cpu_476 string. * config/rs6000/rs6000.md: (define_attr "type"): Add isel attribute. (define_attr "cpu"): Add ppc476. Include 476.md. Update comments for 476. (isel_signed, isel_unsigned): Change to use "isel" type attribute. * config/rs6000/vxworks.h (CPP_SPEC): Handle 464 and 476. Update copyright year. * config/rs6000/476.md: New file. * config/rs6000/40x.md: Add description for "isel" attribute. Update copyright year. * config/rs6000/440.md: Likewise. * config/rs6000/603.md: Likewise. * config/rs6000/6xx.md: Likewise. * config/rs6000/7450.md: Likewise. * config/rs6000/7xx.md: Likewise. * config/rs6000/8540.md: Likewise. * config/rs6000/cell.md: Likewise. * config/rs6000/e300c2c3.md: Likewise. * config/rs6000/e500mc.md: Likewise. * config/rs6000/mpc.md: Likewise. * config/rs6000/power4.md: Likewise. * config/rs6000/power5.md: Likewise. * config/rs6000/power6.md: Likewise. * config/rs6000/power7.md: Likewise. * config/rs6000/rios1.md: Likewise. * config/rs6000/rios2.md: Likewise. * config/rs6000/rs64.md: Likewise. From-SVN: r152626 --- gcc/ChangeLog | 46 +++++++++++ gcc/config.gcc | 4 +- gcc/config.in | 6 ++ gcc/config/rs6000/40x.md | 4 +- gcc/config/rs6000/440.md | 4 +- gcc/config/rs6000/476.md | 142 ++++++++++++++++++++++++++++++++++ gcc/config/rs6000/603.md | 4 +- gcc/config/rs6000/6xx.md | 4 +- gcc/config/rs6000/7450.md | 4 +- gcc/config/rs6000/7xx.md | 4 +- gcc/config/rs6000/8540.md | 4 +- gcc/config/rs6000/cell.md | 4 +- gcc/config/rs6000/e300c2c3.md | 4 +- gcc/config/rs6000/e500mc.md | 2 +- gcc/config/rs6000/mpc.md | 4 +- gcc/config/rs6000/power4.md | 4 +- gcc/config/rs6000/power5.md | 4 +- gcc/config/rs6000/power6.md | 7 +- gcc/config/rs6000/power7.md | 2 +- gcc/config/rs6000/rios1.md | 4 +- gcc/config/rs6000/rios2.md | 4 +- gcc/config/rs6000/rs6000.c | 30 +++++++ gcc/config/rs6000/rs6000.h | 10 +++ gcc/config/rs6000/rs6000.md | 15 ++-- gcc/config/rs6000/rs64.md | 4 +- gcc/config/rs6000/t-fprules | 1 + gcc/config/rs6000/vxworks.h | 4 +- gcc/configure | 44 +++++++++++ gcc/configure.ac | 15 ++++ gcc/doc/invoke.texi | 10 +-- 30 files changed, 351 insertions(+), 47 deletions(-) create mode 100644 gcc/config/rs6000/476.md diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 947dd1f75c37..4bc8600ec055 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,49 @@ +2009-10-10 Peter Bergner + + * configure.ac: Add test for dci instruction. + * configure: Regenerate. + * config.in: Likewise. + * config.gcc: Handle --with-cpu=476 and --with-cpu=476fp. + * doc/invoke.texi: Add cpu_type 476 and 476fp. + (-mmulhw): Add 476 to description. + (-mdlmzb): Likewise. + * config/rs6000/t-fprules (MULTILIB_MATCHES_FLOAT): Include -mcpu=476. + * config/rs6000/rs6000.c (processor_costs): Add ppc476_cost. + (processor_target_table): Add 476 and 476fp entries. + (rs6000_override_options): Use ppc476_cost for PROCESSOR_PPC476. + (rs6000_issue_rate): Add CPU_PPC476. + * config/rs6000/rs6000.h (ASM_CPU_476_SPEC): Define. + (ASM_CPU_SPEC): Pass %(asm_cpu_476) for -mcpu=476 and -mcpu=476fp. + (processor_type): Add PROCESSOR_PPC476. + (EXTRA_SPECS): Add asm_cpu_476 string. + * config/rs6000/rs6000.md: (define_attr "type"): Add isel attribute. + (define_attr "cpu"): Add ppc476. + Include 476.md. + Update comments for 476. + (isel_signed, isel_unsigned): Change to use "isel" type attribute. + * config/rs6000/vxworks.h (CPP_SPEC): Handle 464 and 476. + Update copyright year. + * config/rs6000/476.md: New file. + * config/rs6000/40x.md: Add description for "isel" attribute. + Update copyright year. + * config/rs6000/440.md: Likewise. + * config/rs6000/603.md: Likewise. + * config/rs6000/6xx.md: Likewise. + * config/rs6000/7450.md: Likewise. + * config/rs6000/7xx.md: Likewise. + * config/rs6000/8540.md: Likewise. + * config/rs6000/cell.md: Likewise. + * config/rs6000/e300c2c3.md: Likewise. + * config/rs6000/e500mc.md: Likewise. + * config/rs6000/mpc.md: Likewise. + * config/rs6000/power4.md: Likewise. + * config/rs6000/power5.md: Likewise. + * config/rs6000/power6.md: Likewise. + * config/rs6000/power7.md: Likewise. + * config/rs6000/rios1.md: Likewise. + * config/rs6000/rios2.md: Likewise. + * config/rs6000/rs64.md: Likewise. + 2009-10-10 Richard Guenther PR tree-optimization/41654 diff --git a/gcc/config.gcc b/gcc/config.gcc index 8f794d4ef9e5..e83382c10594 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -3066,8 +3066,8 @@ case "${target}" in | power | power[234567] | power6x | powerpc | powerpc64 \ | rios | rios1 | rios2 | rsc | rsc1 | rs64a \ | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \ - | 505 | 601 | 602 | 603 | 603e | ec603e | 604 \ - | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \ + | 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \ + | 604 | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \ | a2 | e300c[23] | 854[08] | e500mc \ | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell) # OK diff --git a/gcc/config.in b/gcc/config.in index 220ff9f2ae2f..4c3da5baed7c 100644 --- a/gcc/config.in +++ b/gcc/config.in @@ -211,6 +211,12 @@ #endif +/* Define if your assembler supports the DCI/ICI instructions. */ +#ifndef USED_FOR_TARGET +#undef HAVE_AS_DCI +#endif + + /* Define if your assembler supports the --debug-prefix-map option. */ #ifndef USED_FOR_TARGET #undef HAVE_AS_DEBUG_PREFIX_MAP diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md index e11c6539f68b..eaf1222eca42 100644 --- a/gcc/config/rs6000/40x.md +++ b/gcc/config/rs6000/40x.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM PowerPC 403 and PowerPC 405 processors. -;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -38,7 +38,7 @@ (define_insn_reservation "ppc403-integer" 1 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ - var_shift_rotate,cntlz,exts") + var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc403,ppc405")) "iu_40x") diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md index b146222ac506..b329e7897cdd 100644 --- a/gcc/config/rs6000/440.md +++ b/gcc/config/rs6000/440.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM PowerPC 440 processor. -;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -55,7 +55,7 @@ (define_insn_reservation "ppc440-integer" 1 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\ - trap,var_shift_rotate,cntlz,exts") + trap,var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc440")) "ppc440_issue,ppc440_i_pipe|ppc440_j_pipe") diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md new file mode 100644 index 000000000000..3f50bafa03c2 --- /dev/null +++ b/gcc/config/rs6000/476.md @@ -0,0 +1,142 @@ +;; Scheduling description for IBM PowerPC 476 processor. +;; Copyright (C) 2009 +;; Free Software Foundation, Inc. +;; Contributed by Peter Bergner (bergner@vnet.ibm.com). +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; PPC476 Embedded PowerPC controller +;; 3 issue (476) / 4 issue (476fp) +;; +;; i_pipe - complex integer / compare +;; lj_pipe - load-store / simple integer arithmetic +;; b_pipe - branch pipe +;; f_pipe - floating point arithmetic + +(define_automaton "ppc476_core,ppc476_apu") + +(define_cpu_unit "ppc476_i_pipe,ppc476_lj_pipe,ppc476_b_pipe" "ppc476_core") +(define_cpu_unit "ppc476_issue_fp,ppc476_f_pipe" "ppc476_apu") +(define_cpu_unit "ppc476_issue_0,ppc476_issue_1,ppc476_issue_2" "ppc476_core") + +(define_reservation "ppc476_issue" "ppc476_issue_0|ppc476_issue_1|ppc476_issue_2") +(define_reservation "ppc476_issue2" "ppc476_issue_0+ppc476_issue_1\ + |ppc476_issue_0+ppc476_issue_2\ + |ppc476_issue_1+ppc476_issue_2") +(define_reservation "ppc476_issue3" "ppc476_issue_0+ppc476_issue_1+ppc476_issue_2") + +(define_insn_reservation "ppc476-load" 4 + (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ + load_l,store_c,sync") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_lj_pipe") + +(define_insn_reservation "ppc476-store" 4 + (and (eq_attr "type" "store,store_ux,store_u") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_lj_pipe") + +(define_insn_reservation "ppc476-fpload" 4 + (and (eq_attr "type" "fpload,fpload_ux,fpload_u") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_lj_pipe") + +(define_insn_reservation "ppc476-fpstore" 4 + (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_lj_pipe") + +(define_insn_reservation "ppc476-simple-integer" 1 + (and (eq_attr "type" "integer,insert_word,var_shift_rotate,exts,shift") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_i_pipe|ppc476_lj_pipe") + +(define_insn_reservation "ppc476-complex-integer" 1 + (and (eq_attr "type" "cmp,cr_logical,delayed_cr,cntlz,isel,isync,sync,trap") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_i_pipe") + +(define_insn_reservation "ppc476-compare" 4 + (and (eq_attr "type" "compare,delayed_compare,fast_compare,mfcr,mfcrf,\ + mtcr,mfjmpr,mtjmpr,var_delayed_compare") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_i_pipe") + +(define_insn_reservation "ppc476-imul" 4 + (and (eq_attr "type" "imul,imul_compare,imul2,imul3") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_i_pipe") + +(define_insn_reservation "ppc476-idiv" 11 + (and (eq_attr "type" "idiv") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_i_pipe*11") + +(define_insn_reservation "ppc476-branch" 1 + (and (eq_attr "type" "branch,jmpreg") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_b_pipe") + +(define_insn_reservation "ppc476-two" 2 + (and (eq_attr "type" "two") + (eq_attr "cpu" "ppc476")) + "ppc476_issue2,\ + ppc476_i_pipe|ppc476_lj_pipe,\ + ppc476_i_pipe|ppc476_lj_pipe") + +(define_insn_reservation "ppc476-three" 3 + (and (eq_attr "type" "three") + (eq_attr "cpu" "ppc476")) + "ppc476_issue3,\ + ppc476_i_pipe|ppc476_lj_pipe,\ + ppc476_i_pipe|ppc476_lj_pipe,\ + ppc476_i_pipe|ppc476_lj_pipe") + +(define_insn_reservation "ppc476-fpcompare" 6 + (and (eq_attr "type" "fpcompare") + (eq_attr "cpu" "ppc476")) + "ppc476_issue+ppc476_issue_fp,\ + ppc476_f_pipe+ppc476_i_pipe") + +(define_insn_reservation "ppc476-fp" 6 + (and (eq_attr "type" "fp,dmul") + (eq_attr "cpu" "ppc476")) + "ppc476_issue_fp,\ + ppc476_f_pipe") + +(define_insn_reservation "ppc476-sdiv" 19 + (and (eq_attr "type" "sdiv") + (eq_attr "cpu" "ppc476")) + "ppc476_issue_fp, + ppc476_f_pipe*19") + +(define_insn_reservation "ppc476-ddiv" 33 + (and (eq_attr "type" "ddiv") + (eq_attr "cpu" "ppc476")) + "ppc476_issue_fp,\ + ppc476_f_pipe*33") + diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md index c5fea3148193..a042729a1daa 100644 --- a/gcc/config/rs6000/603.md +++ b/gcc/config/rs6000/603.md @@ -1,5 +1,5 @@ ;; Scheduling description for PowerPC 603 processor. -;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -59,7 +59,7 @@ (define_insn_reservation "ppc603-integer" 1 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ - var_shift_rotate,cntlz,exts") + var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc603")) "iu_603") diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md index 88c15ae39ec5..b0de9731525e 100644 --- a/gcc/config/rs6000/6xx.md +++ b/gcc/config/rs6000/6xx.md @@ -1,6 +1,6 @@ ;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620, ;; and PowerPC 630 processors. -;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -74,7 +74,7 @@ (define_insn_reservation "ppc604-integer" 1 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ - var_shift_rotate,cntlz,exts") + var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) "iu1_6xx|iu2_6xx") diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md index 6f2775744d49..ccaa3b20da3b 100644 --- a/gcc/config/rs6000/7450.md +++ b/gcc/config/rs6000/7450.md @@ -1,5 +1,5 @@ ;; Scheduling description for Motorola PowerPC 7450 processor. -;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -75,7 +75,7 @@ (define_insn_reservation "ppc7450-integer" 1 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\ - trap,var_shift_rotate,cntlz,exts") + trap,var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc7450")) "ppc7450_du,iu1_7450|iu2_7450|iu3_7450") diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md index 0129048c07cd..edbde75c22af 100644 --- a/gcc/config/rs6000/7xx.md +++ b/gcc/config/rs6000/7xx.md @@ -1,5 +1,5 @@ ;; Scheduling description for Motorola PowerPC 750 and PowerPC 7400 processors. -;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -65,7 +65,7 @@ (define_insn_reservation "ppc750-integer" 1 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\ - trap,var_shift_rotate,cntlz,exts") + trap,var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc750,ppc7400")) "ppc750_du,iu1_7xx|iu2_7xx") diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md index 2d44b3af94bf..4096dff432c0 100644 --- a/gcc/config/rs6000/8540.md +++ b/gcc/config/rs6000/8540.md @@ -1,5 +1,5 @@ ;; Pipeline description for Motorola PowerPC 8540 processor. -;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -86,7 +86,7 @@ (define_insn_reservation "ppc8540_su" 1 (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\ delayed_compare,var_delayed_compare,fast_compare,\ - shift,trap,var_shift_rotate,cntlz,exts") + shift,trap,var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc8540")) "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md index 3fffd2740f9f..dac9da943209 100644 --- a/gcc/config/rs6000/cell.md +++ b/gcc/config/rs6000/cell.md @@ -1,5 +1,5 @@ ;; Scheduling description for cell processor. -;; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007 +;; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009 ;; Free Software Foundation, Inc. ;; Contributed by Sony Computer Entertainment, Inc., @@ -157,7 +157,7 @@ ;; Integer latency is 2 cycles (define_insn_reservation "cell-integer" 2 (and (eq_attr "type" "integer,insert_dword,shift,trap,\ - var_shift_rotate,cntlz,exts") + var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "cell")) "slot01,fxu_cell") diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md index 31bf14ce3142..3462a209f74b 100644 --- a/gcc/config/rs6000/e300c2c3.md +++ b/gcc/config/rs6000/e300c2c3.md @@ -1,5 +1,5 @@ ;; Pipeline description for Motorola PowerPC e300c3 core. -;; Copyright (C) 2008 Free Software Foundation, Inc. +;; Copyright (C) 2008, 2009 Free Software Foundation, Inc. ;; Contributed by Edmar Wienskoski (edmar@freescale.com) ;; ;; This file is part of GCC. @@ -90,7 +90,7 @@ ;; Other one cycle IU insns (define_insn_reservation "ppce300c3_iu" 1 - (and (eq_attr "type" "integer,insert_word") + (and (eq_attr "type" "integer,insert_word,isel") (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire") diff --git a/gcc/config/rs6000/e500mc.md b/gcc/config/rs6000/e500mc.md index 86434f95fe1d..99a4b80ecf69 100644 --- a/gcc/config/rs6000/e500mc.md +++ b/gcc/config/rs6000/e500mc.md @@ -72,7 +72,7 @@ (define_insn_reservation "e500mc_su" 1 (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\ delayed_compare,var_delayed_compare,fast_compare,\ - shift,trap,var_shift_rotate,cntlz,exts") + shift,trap,var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppce500mc")) "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire") diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md index a839f936648c..415c68872324 100644 --- a/gcc/config/rs6000/mpc.md +++ b/gcc/config/rs6000/mpc.md @@ -1,5 +1,5 @@ ;; Scheduling description for Motorola PowerPC processor cores. -;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -43,7 +43,7 @@ (define_insn_reservation "mpccore-integer" 1 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ - var_shift_rotate,cntlz,exts") + var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "mpccore")) "iu_mpc") diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md index 0214c98b139d..60dbffd58c99 100644 --- a/gcc/config/rs6000/power4.md +++ b/gcc/config/rs6000/power4.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM Power4 and PowerPC 970 processors. -;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -188,7 +188,7 @@ ; Integer latency is 2 cycles (define_insn_reservation "power4-integer" 2 (and (eq_attr "type" "integer,insert_dword,shift,trap,\ - var_shift_rotate,cntlz,exts") + var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "power4")) "iq_power4") diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md index 83ffabcfb3a4..b6db0931219d 100644 --- a/gcc/config/rs6000/power5.md +++ b/gcc/config/rs6000/power5.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM POWER5 processor. -;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -142,7 +142,7 @@ ; Integer latency is 2 cycles (define_insn_reservation "power5-integer" 2 (and (eq_attr "type" "integer,insert_dword,shift,trap,\ - var_shift_rotate,cntlz,exts") + var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "power5")) "iq_power5") diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md index ba6524cfa65c..8d54c8129632 100644 --- a/gcc/config/rs6000/power6.md +++ b/gcc/config/rs6000/power6.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM POWER6 processor. -;; Copyright (C) 2006, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2006, 2007, 2009 Free Software Foundation, Inc. ;; Contributed by Peter Steinmetz (steinmtz@us.ibm.com) ;; ;; This file is part of GCC. @@ -201,6 +201,11 @@ (eq_attr "cpu" "power6")) "FXU_power6") +(define_insn_reservation "power6-isel" 1 + (and (eq_attr "type" "isel") + (eq_attr "cpu" "power6")) + "FXU_power6") + (define_insn_reservation "power6-exts" 1 (and (eq_attr "type" "exts") (eq_attr "cpu" "power6")) diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md index 3b6a95e284e9..148a7a52a8a5 100644 --- a/gcc/config/rs6000/power7.md +++ b/gcc/config/rs6000/power7.md @@ -150,7 +150,7 @@ ; FX Unit (define_insn_reservation "power7-integer" 1 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ - var_shift_rotate,exts") + var_shift_rotate,exts,isel") (eq_attr "cpu" "power7")) "DU_power7,FXU_power7") diff --git a/gcc/config/rs6000/rios1.md b/gcc/config/rs6000/rios1.md index be2262d12815..9ad9ce3e161a 100644 --- a/gcc/config/rs6000/rios1.md +++ b/gcc/config/rs6000/rios1.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM POWER processor. -;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -52,7 +52,7 @@ (define_insn_reservation "rios1-integer" 1 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\ - trap,var_shift_rotate,cntlz,exts") + trap,var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "rios1,ppc601")) "iu_rios1") diff --git a/gcc/config/rs6000/rios2.md b/gcc/config/rs6000/rios2.md index 24fbc15b9add..96633af2f8ea 100644 --- a/gcc/config/rs6000/rios2.md +++ b/gcc/config/rs6000/rios2.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM Power2 processor. -;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -40,7 +40,7 @@ (define_insn_reservation "rios2-integer" 1 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ - var_shift_rotate,cntlz,exts") + var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "rios2")) "iu1_rios2|iu2_rios2") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 319af631933f..dea4a5334b05 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -511,6 +511,25 @@ struct processor_costs ppc440_cost = { 1, /* streams */ }; +/* Instruction costs on PPC476 processors. */ +static const +struct processor_costs ppc476_cost = { + COSTS_N_INSNS (4), /* mulsi */ + COSTS_N_INSNS (4), /* mulsi_const */ + COSTS_N_INSNS (4), /* mulsi_const9 */ + COSTS_N_INSNS (4), /* muldi */ + COSTS_N_INSNS (11), /* divsi */ + COSTS_N_INSNS (11), /* divdi */ + COSTS_N_INSNS (6), /* fp */ + COSTS_N_INSNS (6), /* dmul */ + COSTS_N_INSNS (19), /* sdiv */ + COSTS_N_INSNS (33), /* ddiv */ + 32, /* l1 cache line size */ + 32, /* l1 cache */ + 512, /* l2 cache */ + 1, /* streams */ +}; + /* Instruction costs on PPC601 processors. */ static const struct processor_costs ppc601_cost = { @@ -2144,6 +2163,12 @@ rs6000_override_options (const char *default_cpu) POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB}, {"464fp", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB}, + {"476", PROCESSOR_PPC476, + POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF + | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB}, + {"476fp", PROCESSOR_PPC476, + POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB + | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB}, {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK}, {"601", PROCESSOR_PPC601, MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING}, @@ -2673,6 +2698,10 @@ rs6000_override_options (const char *default_cpu) rs6000_cost = &ppc440_cost; break; + case PROCESSOR_PPC476: + rs6000_cost = &ppc476_cost; + break; + case PROCESSOR_PPC601: rs6000_cost = &ppc601_cost; break; @@ -21795,6 +21824,7 @@ rs6000_issue_rate (void) case CPU_PPCE500MC: return 2; case CPU_RIOS2: + case CPU_PPC476: case CPU_PPC604: case CPU_PPC604E: case CPU_PPC620: diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index a5ce9dd0f7f6..c8ab4369a396 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -83,6 +83,12 @@ #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" #endif +#ifdef HAVE_AS_DCI +#define ASM_CPU_476_SPEC "-m476" +#else +#define ASM_CPU_476_SPEC "-mpower4" +#endif + /* Common ASM definitions used by ASM_SPEC among the various targets for handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to provide the default assembler options if the user uses -mcpu=native, so if @@ -123,6 +129,8 @@ %{mcpu=440fp: -m440} \ %{mcpu=464: -m440} \ %{mcpu=464fp: -m440} \ +%{mcpu=476: %(asm_cpu_476)} \ +%{mcpu=476fp: %(asm_cpu_476)} \ %{mcpu=505: -mppc} \ %{mcpu=601: -m601} \ %{mcpu=602: -mppc} \ @@ -178,6 +186,7 @@ { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ + { "asm_cpu_476", ASM_CPU_476_SPEC }, \ SUBTARGET_EXTRA_SPECS /* -mcpu=native handling only makes sense with compiler running on @@ -318,6 +327,7 @@ enum processor_type PROCESSOR_PPC403, PROCESSOR_PPC405, PROCESSOR_PPC440, + PROCESSOR_PPC476, PROCESSOR_PPC601, PROCESSOR_PPC603, PROCESSOR_PPC604, diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 7b3de2ad230a..7ff1b3c1a477 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -117,7 +117,7 @@ ;; Define an insn type attribute. This is used in function unit delay ;; computations. -(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr" +(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel" (const_string "integer")) ;; Define floating point instruction sub-types for use with Xfpu.md @@ -139,7 +139,7 @@ ;; Processor type -- this attribute must exactly match the processor_type ;; enumeration in rs6000.h. -(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,power7,cell,ppca2" +(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,power7,cell,ppca2" (const (symbol_ref "rs6000_cpu_attr"))) @@ -158,6 +158,7 @@ (include "mpc.md") (include "40x.md") (include "440.md") +(include "476.md") (include "603.md") (include "6xx.md") (include "7xx.md") @@ -975,7 +976,7 @@ [(set_attr "type" "compare") (set_attr "length" "4,8")]) -;; IBM 405, 440 and 464 half-word multiplication operations. +;; IBM 405, 440, 464 and 476 half-word multiplication operations. (define_insn "*macchwc" [(set (match_operand:CC 3 "cc_reg_operand" "=x") @@ -1439,7 +1440,7 @@ "mullhwu %0, %1, %2" [(set_attr "type" "imul3")]) -;; IBM 405, 440 and 464 string-search dlmzb instruction support. +;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support. (define_insn "dlmzb" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") @@ -6041,7 +6042,8 @@ "TARGET_ISEL" "* { return output_isel (operands); }" - [(set_attr "length" "4")]) + [(set_attr "type" "isel") + (set_attr "length" "4")]) (define_insn "isel_unsigned_" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") @@ -6054,7 +6056,8 @@ "TARGET_ISEL" "* { return output_isel (operands); }" - [(set_attr "length" "4")]) + [(set_attr "type" "isel") + (set_attr "length" "4")]) (define_expand "movsfcc" [(set (match_operand:SF 0 "gpc_reg_operand" "") diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md index f7234408ade4..e221b52a3709 100644 --- a/gcc/config/rs6000/rs64.md +++ b/gcc/config/rs6000/rs64.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM RS64 processors. -;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -47,7 +47,7 @@ (define_insn_reservation "rs64a-integer" 1 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ - var_shift_rotate,cntlz,exts") + var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "rs64a")) "iu_rs64") diff --git a/gcc/config/rs6000/t-fprules b/gcc/config/rs6000/t-fprules index 272e00c1adab..42d8fd77b5b0 100644 --- a/gcc/config/rs6000/t-fprules +++ b/gcc/config/rs6000/t-fprules @@ -21,6 +21,7 @@ MULTILIB_MATCHES_FLOAT = msoft-float=mcpu?401 \ msoft-float=mcpu?405 \ msoft-float=mcpu?440 \ msoft-float=mcpu?464 \ + msoft-float=mcpu?476 \ msoft-float=mcpu?ec603e \ msoft-float=mcpu?801 \ msoft-float=mcpu?821 \ diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index cfd11eb6d798..c302ad2015d3 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. Vxworks PowerPC version. - Copyright (C) 1996, 2000, 2002, 2003, 2004, 2005, 2007 + Copyright (C) 1996, 2000, 2002, 2003, 2004, 2005, 2007, 2009 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. @@ -68,6 +68,8 @@ along with GCC; see the file COPYING3. If not see %{mcpu=403 : -DCPU=PPC403 ; \ mcpu=405 : -DCPU=PPC405 ; \ mcpu=440 : -DCPU=PPC440 ; \ + mcpu=464 : -DCPU=PPC464 ; \ + mcpu=476 : -DCPU=PPC476 ; \ mcpu=603 : -DCPU=PPC603 ; \ mcpu=604 : -DCPU=PPC604 ; \ mcpu=860 : -DCPU=PPC860 ; \ diff --git a/gcc/configure b/gcc/configure index 903c949ce6b8..66b38ec99a1b 100755 --- a/gcc/configure +++ b/gcc/configure @@ -23513,6 +23513,50 @@ if test $gcc_cv_as_powerpc_lwsync = yes; then $as_echo "#define HAVE_AS_LWSYNC 1" >>confdefs.h +fi + + case $target in + *-*-aix*) conftest_s=' .machine "476" + .csect .text[PR] + dci 0';; + *) conftest_s=' .machine "476" + .text + dci 0';; + esac + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for data cache invalidate support" >&5 +$as_echo_n "checking assembler for data cache invalidate support... " >&6; } +if test "${gcc_cv_as_powerpc_dci+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + gcc_cv_as_powerpc_dci=no + if test $in_tree_gas = yes; then + if test $gcc_cv_gas_vers -ge `expr \( \( 9 \* 1000 \) + 99 \) \* 1000 + 0` + then gcc_cv_as_powerpc_dci=yes +fi + elif test x$gcc_cv_as != x; then + echo "$conftest_s" > conftest.s + if { ac_try='$gcc_cv_as -a32 -o conftest.o conftest.s >&5' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; } + then + gcc_cv_as_powerpc_dci=yes + else + echo "configure: failed program was" >&5 + cat conftest.s >&5 + fi + rm -f conftest.o conftest.s + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_powerpc_dci" >&5 +$as_echo "$gcc_cv_as_powerpc_dci" >&6; } +if test $gcc_cv_as_powerpc_dci = yes; then + +$as_echo "#define HAVE_AS_DCI 1" >>confdefs.h + fi { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .gnu_attribute support" >&5 diff --git a/gcc/configure.ac b/gcc/configure.ac index eee47ad08b4a..7947d2856299 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -3249,6 +3249,21 @@ LCF0: [AC_DEFINE(HAVE_AS_LWSYNC, 1, [Define if your assembler supports LWSYNC instructions.])]) + case $target in + *-*-aix*) conftest_s=' .machine "476" + .csect .text[[PR]] + dci 0';; + *) conftest_s=' .machine "476" + .text + dci 0';; + esac + + gcc_GAS_CHECK_FEATURE([data cache invalidate support], + gcc_cv_as_powerpc_dci, [9,99,0], -a32, + [$conftest_s],, + [AC_DEFINE(HAVE_AS_DCI, 1, + [Define if your assembler supports the DCI/ICI instructions.])]) + gcc_GAS_CHECK_FEATURE([.gnu_attribute support], gcc_cv_as_powerpc_gnu_attribute, [2,18,0],, [.gnu_attribute 4,1],, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index da7afeaba1e9..3f131fd02b4a 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14606,9 +14606,9 @@ Set architecture type, register usage, choice of mnemonics, and instruction scheduling parameters for machine type @var{cpu_type}. Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{464}, @samp{464fp}, -@samp{505}, @samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604}, -@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400}, -@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823}, +@samp{476}, @samp{476fp}, @samp{505}, @samp{601}, @samp{602}, @samp{603}, +@samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{630}, @samp{740}, +@samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823}, @samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2}, @samp{e300c3}, @samp{e500mc}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3}, @samp{power4}, @@ -14954,7 +14954,7 @@ hardware floating is used. @opindex mmulhw @opindex mno-mulhw Generate code that uses (does not use) the half-word multiply and -multiply-accumulate instructions on the IBM 405, 440 and 464 processors. +multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors. These instructions are generated by default when targetting those processors. @@ -14963,7 +14963,7 @@ processors. @opindex mdlmzb @opindex mno-dlmzb Generate code that uses (does not use) the string-search @samp{dlmzb} -instruction on the IBM 405, 440 and 464 processors. This instruction is +instruction on the IBM 405, 440, 464 and 476 processors. This instruction is generated by default when targetting those processors. @item -mno-bit-align