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vmull / vmovl support for Neon.
For Tejas Belagod 2010-08-25 Tejas Belagod <tejas.belagod@arm.com> * lib/target-supports.exp (check_effective_target_vect_unpack): Set vect_unpack supported flag to true for neon. * config/arm/iterators.md (VU, SE, V_widen_l): New. (V_unpack, US): New. * config/arm/neon.md (vec_unpack<US>_hi_<mode>): Expansion for vmovl. (vec_unpack<US>_lo_<mode>): Likewise. (neon_vec_unpack<US>_hi_<mode>): Instruction pattern for vmovl. (neon_vec_unpack<US>_lo_<mode>): Likewise. (vec_widen_<US>mult_lo_<mode>): Expansion for vmull. (vec_widen_<US>mult_hi_<mode>): Likewise. (neon_vec_<US>mult_lo_<mode>"): Instruction pattern for vmull. (neon_vec_<US>mult_hi_<mode>"): Likewise. (neon_unpack<US>_<mode>): Widening move intermediate step for vectorizing without -mvectorize-with-neon-quad. (neon_vec_<US>mult_<mode>): Widening multiply intermediate step for vectorizing without -mvectorize-with-neon-quad. * config/arm/predicates.md (vect_par_constant_high): Check for high-half lanes of a vector. (vect_par_constant_low): Check for low-half lanes of a vector. From-SVN: r163538
This commit is contained in:
Tejas Belagod
Ramana Radhakrishnan
parent
34f41f7c1a
commit
46b57af175
@ -1,3 +1,24 @@
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2010-08-25 Tejas Belagod <tejas.belagod@arm.com>
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* config/arm/iterators.md (VU, SE, V_widen_l): New.
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(V_unpack, US): New.
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* config/arm/neon.md (vec_unpack<US>_hi_<mode>): Expansion for
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vmovl.
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(vec_unpack<US>_lo_<mode>): Likewise.
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(neon_vec_unpack<US>_hi_<mode>): Instruction pattern for vmovl.
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(neon_vec_unpack<US>_lo_<mode>): Likewise.
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(vec_widen_<US>mult_lo_<mode>): Expansion for vmull.
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(vec_widen_<US>mult_hi_<mode>): Likewise.
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(neon_vec_<US>mult_lo_<mode>"): Instruction pattern for vmull.
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(neon_vec_<US>mult_hi_<mode>"): Likewise.
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(neon_unpack<US>_<mode>): Widening move intermediate step for
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vectorizing without -mvectorize-with-neon-quad.
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(neon_vec_<US>mult_<mode>): Widening multiply intermediate step
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for vectorizing without -mvectorize-with-neon-quad.
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* config/arm/predicates.md (vect_par_constant_high): Check for
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high-half lanes of a vector.
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(vect_par_constant_low): Check for low-half lanes of a vector.
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2010-08-24 Sebastian Pop <sebastian.pop@amd.com>
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* tree-if-conv.c (struct ifc_dr): New.
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@ -136,7 +136,9 @@
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;; Modes with 32-bit elements only.
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(define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
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;; Modes with 8-bit, 16-bit and 32-bit elements.
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(define_mode_iterator VU [V16QI V8HI V4SI])
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;;----------------------------------------------------------------------------
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;; Code iterators
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;;----------------------------------------------------------------------------
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@ -156,6 +158,8 @@
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;; without unsigned variants (for use with *SFmode pattern).
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(define_code_iterator vqhs_ops [plus smin smax])
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;; A list of widening operators
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(define_code_iterator SE [sign_extend zero_extend])
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;;----------------------------------------------------------------------------
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;; Mode attributes
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@ -360,6 +364,11 @@
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(V2SF "2") (V4SF "4")
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(DI "1") (V2DI "2")])
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;; Same as V_widen, but lower-case.
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(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")])
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;; Widen. Result is half the number of elements, but widened to double-width.
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(define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
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;;----------------------------------------------------------------------------
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;; Code attributes
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@ -375,3 +384,6 @@
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(define_code_attr cnb [(ltu "CC_C") (geu "CC")])
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(define_code_attr optab [(ltu "ltu") (geu "geu")])
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;; Assembler mnemonics for signedness of widening operations.
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(define_code_attr US [(sign_extend "s") (zero_extend "u")])
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@ -4977,3 +4977,205 @@
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emit_insn (gen_orn<mode>3_neon (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_insn "neon_vec_unpack<US>_lo_<mode>"
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[(set (match_operand:<V_unpack> 0 "register_operand" "=w")
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(SE:<V_unpack> (vec_select:<V_HALF>
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(match_operand:VU 1 "register_operand" "w")
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(match_operand:VU 2 "vect_par_constant_low" ""))))]
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"TARGET_NEON"
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"vmovl.<US><V_sz_elem> %q0, %e1"
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[(set_attr "neon_type" "neon_shift_1")]
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)
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(define_insn "neon_vec_unpack<US>_hi_<mode>"
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[(set (match_operand:<V_unpack> 0 "register_operand" "=w")
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(SE:<V_unpack> (vec_select:<V_HALF>
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(match_operand:VU 1 "register_operand" "w")
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(match_operand:VU 2 "vect_par_constant_high" ""))))]
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"TARGET_NEON"
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"vmovl.<US><V_sz_elem> %q0, %f1"
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[(set_attr "neon_type" "neon_shift_1")]
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)
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(define_expand "vec_unpack<US>_hi_<mode>"
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[(match_operand:<V_unpack> 0 "register_operand" "")
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(SE:<V_unpack> (match_operand:VU 1 "register_operand"))]
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"TARGET_NEON"
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{
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rtvec v = rtvec_alloc (<V_mode_nunits>/2) ;
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rtx t1;
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int i;
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for (i = 0; i < (<V_mode_nunits>/2); i++)
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RTVEC_ELT (v, i) = GEN_INT ((<V_mode_nunits>/2) + i);
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t1 = gen_rtx_PARALLEL (<MODE>mode, v);
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emit_insn (gen_neon_vec_unpack<US>_hi_<mode> (operands[0],
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operands[1],
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t1));
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DONE;
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}
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)
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(define_expand "vec_unpack<US>_lo_<mode>"
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[(match_operand:<V_unpack> 0 "register_operand" "")
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(SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))]
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"TARGET_NEON"
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{
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rtvec v = rtvec_alloc (<V_mode_nunits>/2) ;
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rtx t1;
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int i;
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for (i = 0; i < (<V_mode_nunits>/2) ; i++)
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RTVEC_ELT (v, i) = GEN_INT (i);
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t1 = gen_rtx_PARALLEL (<MODE>mode, v);
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emit_insn (gen_neon_vec_unpack<US>_lo_<mode> (operands[0],
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operands[1],
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t1));
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DONE;
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}
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)
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(define_insn "neon_vec_<US>mult_lo_<mode>"
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[(set (match_operand:<V_unpack> 0 "register_operand" "=w")
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(mult:<V_unpack> (SE:<V_unpack> (vec_select:<V_HALF>
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(match_operand:VU 1 "register_operand" "w")
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(match_operand:VU 2 "vect_par_constant_low" "")))
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(SE:<V_unpack> (vec_select:<V_HALF>
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(match_operand:VU 3 "register_operand" "w")
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(match_dup 2)))))]
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"TARGET_NEON"
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"vmull.<US><V_sz_elem> %q0, %e1, %e3"
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[(set_attr "neon_type" "neon_shift_1")]
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)
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(define_expand "vec_widen_<US>mult_lo_<mode>"
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[(match_operand:<V_unpack> 0 "register_operand" "")
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(SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))
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(SE:<V_unpack> (match_operand:VU 2 "register_operand" ""))]
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"TARGET_NEON"
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{
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rtvec v = rtvec_alloc (<V_mode_nunits>/2) ;
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rtx t1;
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int i;
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for (i = 0; i < (<V_mode_nunits>/2) ; i++)
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RTVEC_ELT (v, i) = GEN_INT (i);
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t1 = gen_rtx_PARALLEL (<MODE>mode, v);
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emit_insn (gen_neon_vec_<US>mult_lo_<mode> (operands[0],
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operands[1],
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t1,
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operands[2]));
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DONE;
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}
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)
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(define_insn "neon_vec_<US>mult_hi_<mode>"
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[(set (match_operand:<V_unpack> 0 "register_operand" "=w")
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(mult:<V_unpack> (SE:<V_unpack> (vec_select:<V_HALF>
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(match_operand:VU 1 "register_operand" "w")
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(match_operand:VU 2 "vect_par_constant_high" "")))
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(SE:<V_unpack> (vec_select:<V_HALF>
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(match_operand:VU 3 "register_operand" "w")
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(match_dup 2)))))]
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"TARGET_NEON"
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"vmull.<US><V_sz_elem> %q0, %f1, %f3"
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[(set_attr "neon_type" "neon_shift_1")]
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)
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(define_expand "vec_widen_<US>mult_hi_<mode>"
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[(match_operand:<V_unpack> 0 "register_operand" "")
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(SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))
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(SE:<V_unpack> (match_operand:VU 2 "register_operand" ""))]
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"TARGET_NEON"
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{
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rtvec v = rtvec_alloc (<V_mode_nunits>/2) ;
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rtx t1;
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int i;
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for (i = 0; i < (<V_mode_nunits>/2) ; i++)
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RTVEC_ELT (v, i) = GEN_INT (<V_mode_nunits>/2 + i);
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t1 = gen_rtx_PARALLEL (<MODE>mode, v);
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emit_insn (gen_neon_vec_<US>mult_hi_<mode> (operands[0],
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operands[1],
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t1,
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operands[2]));
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DONE;
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}
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)
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;; Vectorize for non-neon-quad case
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(define_insn "neon_unpack<US>_<mode>"
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[(set (match_operand:<V_widen> 0 "register_operand" "=w")
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(SE:<V_widen> (match_operand:VDI 1 "register_operand" "")))]
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"TARGET_NEON"
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"vmovl.<US><V_sz_elem> %q0, %1"
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[(set_attr "neon_type" "neon_shift_1")]
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)
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(define_expand "vec_unpack<US>_lo_<mode>"
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[(match_operand:<V_double_width> 0 "register_operand" "")
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(SE:<V_double_width>(match_operand:VDI 1 "register_operand"))]
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"TARGET_NEON"
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{
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rtx tmpreg = gen_reg_rtx (<V_widen>mode);
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emit_insn (gen_neon_unpack<US>_<mode> (tmpreg, operands[1]));
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emit_insn (gen_neon_vget_low<V_widen_l> (operands[0], tmpreg));
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DONE;
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}
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)
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(define_expand "vec_unpack<US>_hi_<mode>"
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[(match_operand:<V_double_width> 0 "register_operand" "")
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(SE:<V_double_width>(match_operand:VDI 1 "register_operand"))]
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"TARGET_NEON"
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{
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rtx tmpreg = gen_reg_rtx (<V_widen>mode);
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emit_insn (gen_neon_unpack<US>_<mode> (tmpreg, operands[1]));
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emit_insn (gen_neon_vget_high<V_widen_l> (operands[0], tmpreg));
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DONE;
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}
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)
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(define_insn "neon_vec_<US>mult_<mode>"
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[(set (match_operand:<V_widen> 0 "register_operand" "=w")
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(mult:<V_widen> (SE:<V_widen>
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(match_operand:VDI 1 "register_operand" "w"))
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(SE:<V_widen>
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(match_operand:VDI 2 "register_operand" "w"))))]
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"TARGET_NEON"
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"vmull.<US><V_sz_elem> %q0, %1, %2"
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[(set_attr "neon_type" "neon_shift_1")]
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)
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(define_expand "vec_widen_<US>mult_hi_<mode>"
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[(match_operand:<V_double_width> 0 "register_operand" "")
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(SE:<V_double_width> (match_operand:VDI 1 "register_operand" ""))
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(SE:<V_double_width> (match_operand:VDI 2 "register_operand" ""))]
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"TARGET_NEON"
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{
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rtx tmpreg = gen_reg_rtx (<V_widen>mode);
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emit_insn (gen_neon_vec_<US>mult_<mode> (tmpreg, operands[1], operands[2]));
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emit_insn (gen_neon_vget_high<V_widen_l> (operands[0], tmpreg));
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DONE;
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}
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)
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(define_expand "vec_widen_<US>mult_lo_<mode>"
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[(match_operand:<V_double_width> 0 "register_operand" "")
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(SE:<V_double_width> (match_operand:VDI 1 "register_operand" ""))
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(SE:<V_double_width> (match_operand:VDI 2 "register_operand" ""))]
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"TARGET_NEON"
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{
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rtx tmpreg = gen_reg_rtx (<V_widen>mode);
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emit_insn (gen_neon_vec_<US>mult_<mode> (tmpreg, operands[1], operands[2]));
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emit_insn (gen_neon_vget_low<V_widen_l> (operands[0], tmpreg));
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DONE;
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}
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)
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@ -619,3 +619,61 @@
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(and (match_test "TARGET_32BIT")
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(match_operand 0 "arm_di_operand"))))
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;; Predicates for parallel expanders based on mode.
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(define_special_predicate "vect_par_constant_high"
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(match_code "parallel")
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{
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HOST_WIDE_INT count = XVECLEN (op, 0);
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int i;
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int base = GET_MODE_NUNITS (mode);
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if ((count < 1)
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|| (count != base/2))
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return false;
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if (!VECTOR_MODE_P (mode))
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return false;
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for (i = 0; i < count; i++)
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{
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rtx elt = XVECEXP (op, 0, i);
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int val;
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if (GET_CODE (elt) != CONST_INT)
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return false;
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val = INTVAL (elt);
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if (val != (base/2) + i)
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return false;
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}
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return true;
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})
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(define_special_predicate "vect_par_constant_low"
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(match_code "parallel")
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{
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HOST_WIDE_INT count = XVECLEN (op, 0);
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int i;
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int base = GET_MODE_NUNITS (mode);
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if ((count < 1)
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|| (count != base/2))
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return false;
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if (!VECTOR_MODE_P (mode))
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return false;
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for (i = 0; i < count; i++)
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{
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rtx elt = XVECEXP (op, 0, i);
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int val;
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if (GET_CODE (elt) != CONST_INT)
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return false;
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val = INTVAL (elt);
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if (val != i)
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return false;
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}
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return true;
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})
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@ -1,3 +1,8 @@
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2010-08-25 Tejas Belagod <tejas.belagod@arm.com>
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* lib/target-supports.exp (check_effective_target_vect_unpack):
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Set vect_unpack supported flag to true for neon.
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2010-08-24 Sebastian Pop <sebastian.pop@amd.com>
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* gcc.dg/tree-ssa/ifc-5.c: New.
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@ -2640,7 +2640,8 @@ proc check_effective_target_vect_unpack { } {
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if { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*])
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|| [istarget i?86-*-*]
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|| [istarget x86_64-*-*]
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|| [istarget spu-*-*] } {
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|| [istarget spu-*-*]
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|| ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
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set et_vect_unpack_saved 1
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}
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}
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