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A9 integer pipeline description.
2009-10-31 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/cortex-a9.md: New - integer pipeline description.
From-SVN: r153779
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Ramana Radhakrishnan
Ramana Radhakrishnan
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2009-10-31 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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* config/arm/cortex-a9.md: New - integer pipeline description.
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2009-10-31 Eric Botcazou <ebotcazou@adacore.com>
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* tree-ssa-sccvn.c (vn_reference_lookup_3): Bail out instead of
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@ -1,6 +1,8 @@
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;; ARM Cortex-A9 VFP pipeline description
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;; Copyright (C) 2008 Free Software Foundation, Inc.
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;; Written by CodeSourcery.
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;; ARM Cortex-A9 pipeline description
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;; Copyright (C) 2008, 2009 Free Software Foundation, Inc.
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;; Originally written by CodeSourcery for VFP.
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;;
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;; Integer core pipeline description contributed by ARM Ltd.
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;;
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;; This file is part of GCC.
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;;
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(define_automaton "cortex_a9")
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;; FIXME: We model a single pipeline for all instructions.
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;; Is dual-issue possible, and do we have other pipelines?
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(define_cpu_unit "cortex_a9_vfp" "cortex_a9")
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;; The Cortex-A9 integer core is modelled as a dual issue pipeline that has
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;; the following components.
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;; 1. 1 Load Store Pipeline.
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;; 2. P0 / main pipeline for data processing instructions.
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;; 3. P1 / Dual pipeline for Data processing instructions.
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;; 4. MAC pipeline for multiply as well as multiply
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;; and accumulate instructions.
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;; 5. 1 VFP / Neon pipeline.
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;; The Load/Store and VFP/Neon pipeline are multiplexed.
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;; The P0 / main pipeline and M1 stage of the MAC pipeline are
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;; multiplexed.
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;; The P1 / dual pipeline and M2 stage of the MAC pipeline are
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;; multiplexed.
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;; There are only 4 register read ports and hence at any point of
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;; time we can't have issue down the E1 and the E2 ports unless
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;; of course there are bypass paths that get exercised.
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;; Both P0 and P1 have 2 stages E1 and E2.
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;; Data processing instructions issue to E1 or E2 depending on
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;; whether they have an early shift or not.
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(define_cpu_unit "cortex_a9_vfp, cortex_a9_ls" "cortex_a9")
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(define_cpu_unit "cortex_a9_p0_e1, cortex_a9_p0_e2" "cortex_a9")
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(define_cpu_unit "cortex_a9_p1_e1, cortex_a9_p1_e2" "cortex_a9")
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(define_cpu_unit "cortex_a9_p0_wb, cortex_a9_p1_wb" "cortex_a9")
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(define_cpu_unit "cortex_a9_mac_m1, cortex_a9_mac_m2" "cortex_a9")
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(define_cpu_unit "cortex_a9_branch, cortex_a9_issue_branch" "cortex_a9")
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(define_reservation "cortex_a9_p0_default" "cortex_a9_p0_e2, cortex_a9_p0_wb")
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(define_reservation "cortex_a9_p1_default" "cortex_a9_p1_e2, cortex_a9_p1_wb")
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(define_reservation "cortex_a9_p0_shift" "cortex_a9_p0_e1, cortex_a9_p0_default")
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(define_reservation "cortex_a9_p1_shift" "cortex_a9_p1_e1, cortex_a9_p1_default")
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(define_reservation "cortex_a9_multcycle1"
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"cortex_a9_p0_e2 + cortex_a9_mac_m1 + cortex_a9_mac_m2 + \
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cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
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(define_reservation "cortex_a9_mult16"
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"cortex_a9_mac_m1, cortex_a9_mac_m2, cortex_a9_p0_wb")
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(define_reservation "cortex_a9_mac16"
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"cortex_a9_multcycle1, cortex_a9_mac_m2, cortex_a9_p0_wb")
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(define_reservation "cortex_a9_mult"
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"cortex_a9_mac_m1*2, cortex_a9_mac_m2, cortex_a9_p0_wb")
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(define_reservation "cortex_a9_mac"
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"cortex_a9_multcycle1*2 ,cortex_a9_mac_m2, cortex_a9_p0_wb")
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;; Issue at the same time along the load store pipeline and
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;; the VFP / Neon pipeline is not possible.
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;; FIXME:: At some point we need to model the issue
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;; of the load store and the vfp being shared rather than anything else.
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(exclusion_set "cortex_a9_ls" "cortex_a9_vfp")
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;; Default data processing instruction without any shift
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;; The only exception to this is the mov instruction
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;; which can go down E2 without any problem.
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(define_insn_reservation "cortex_a9_dp" 2
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(and (eq_attr "tune" "cortexa9")
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(ior (eq_attr "type" "alu")
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(and (eq_attr "type" "alu_shift_reg, alu_shift")
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(eq_attr "insn" "mov"))))
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"cortex_a9_p0_default|cortex_a9_p1_default")
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;; An instruction using the shifter will go down E1.
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(define_insn_reservation "cortex_a9_dp_shift" 3
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(and (eq_attr "tune" "cortexa9")
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(and (eq_attr "type" "alu_shift_reg, alu_shift")
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(not (eq_attr "insn" "mov"))))
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"cortex_a9_p0_shift | cortex_a9_p1_shift")
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;; Loads have a latency of 4 cycles.
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;; We don't model autoincrement instructions. These
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;; instructions use the load store pipeline and 1 of
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;; the E2 units to write back the result of the increment.
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(define_insn_reservation "cortex_a9_load1_2" 4
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(and (eq_attr "tune" "cortexa9")
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(eq_attr "type" "load1, load2, load_byte"))
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"cortex_a9_ls")
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;; Loads multiples and store multiples can't be issued for 2 cycles in a
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;; row. The description below assumes that addresses are 64 bit aligned.
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;; If not, there is an extra cycle latency which is not modelled.
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;; FIXME:: This bit might need to be reworked when we get to
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;; tuning for the VFP because strictly speaking the ldm
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;; is sent to the LSU unit as is and there is only an
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;; issue restriction between the LSU and the VFP/ Neon unit.
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(define_insn_reservation "cortex_a9_load3_4" 5
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(and (eq_attr "tune" "cortexa9")
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(eq_attr "type" "load3, load4"))
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"cortex_a9_ls, cortex_a9_ls")
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(define_insn_reservation "cortex_a9_store1_2" 0
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(and (eq_attr "tune" "cortexa9")
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(eq_attr "type" "store1, store2"))
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"cortex_a9_ls")
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;; Almost all our store multiples use an auto-increment
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;; form. Don't issue back to back load and store multiples
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;; because the load store unit will stall.
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(define_insn_reservation "cortex_a9_store3_4" 0
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(and (eq_attr "tune" "cortexa9")
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(eq_attr "type" "store3, store4"))
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"cortex_a9_ls+(cortex_a9_p0_default | cortex_a9_p1_default), cortex_a9_ls")
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;; We get 16*16 multiply / mac results in 3 cycles.
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(define_insn_reservation "cortex_a9_mult16" 3
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(and (eq_attr "tune" "cortexa9")
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(eq_attr "insn" "smulxy"))
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"cortex_a9_mult16")
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;; The 16*16 mac is slightly different that it
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;; reserves M1 and M2 in the same cycle.
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(define_insn_reservation "cortex_a9_mac16" 3
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(and (eq_attr "tune" "cortexa9")
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(eq_attr "insn" "smlaxy"))
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"cortex_a9_mac16")
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(define_insn_reservation "cortex_a9_multiply" 4
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(and (eq_attr "tune" "cortexa9")
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(eq_attr "insn" "mul"))
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"cortex_a9_mult")
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(define_insn_reservation "cortex_a9_mac" 4
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(and (eq_attr "tune" "cortexa9")
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(eq_attr "insn" "mla"))
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"cortex_a9_mac")
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;; An instruction with a result in E2 can be forwarded
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;; to E2 or E1 or M1 or the load store unit in the next cycle.
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(define_bypass 1 "cortex_a9_dp"
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"cortex_a9_dp_shift, cortex_a9_multiply,
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cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
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cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4")
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(define_bypass 2 "cortex_a9_dp_shift"
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"cortex_a9_dp_shift, cortex_a9_multiply,
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cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
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cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4")
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;; An instruction in the load store pipeline can provide
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;; read access to a DP instruction in the P0 default pipeline
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;; before the writeback stage.
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(define_bypass 3 "cortex_a9_load1_2" "cortex_a9_dp, cortex_a9_load1_2,
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cortex_a9_store3_4, cortex_a9_store1_2")
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(define_bypass 4 "cortex_a9_load3_4" "cortex_a9_dp, cortex_a9_load1_2,
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cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4")
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;; Calls and branches.
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;; Branch instructions
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(define_insn_reservation "cortex_a9_branch" 0
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(and (eq_attr "tune" "cortexa9")
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(eq_attr "type" "branch"))
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"cortex_a9_branch")
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;; Call latencies are essentially 0 but make sure
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;; dual issue doesn't happen i.e the next instruction
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;; starts at the next cycle.
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(define_insn_reservation "cortex_a9_call" 0
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(and (eq_attr "tune" "cortexa9")
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(eq_attr "type" "call"))
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"cortex_a9_issue_branch + cortex_a9_multcycle1 + cortex_a9_ls + cortex_a9_vfp")
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;; Pipelining for VFP instructions.
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(define_insn_reservation "cortex_a9_ffarith" 1
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(and (eq_attr "tune" "cortexa9")
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