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Add memory barriers to the double-checked locking used for static initialization.
libstdc++:
Add memory barriers to the double-checked locking used for static
initialization.
* libsupc++/guard.cc (__test_and_acquire): Define default.
(_GLIBCXX_GUARD_TEST_AND_ACQUIRE, __set_and_release)
(_GLIBCXX_GUARD_SET_AND_RELEASE): Likewise.
(recursion_push, recursion_pop): New abstraction functions.
(__cxa_guard_acquire): Use _GLIBCXX_GUARD_TEST_AND_ACQUIRE.
(__cxa_guard_release): Use _GLIBCXX_GUARD_SET_AND_RELEASE.
* config/cpu/generic/cxxabi_tweaks.h (_GLIBCXX_GUARD_TEST): Rename
from _GLIBCXX_GUARD_ACQUIRE and reverse sense.
(_GLIBCXX_GUARD_SET): Rename from _GLIBCXX_GUARD_RELEASE.
* config/cpu/arm/cxxabi_tweaks.h: Likewise.
* config/cpu/alpha/atomic_word.h (_GLIBCXX_READ_MEM_BARRIER)
(_GLIBCXX_WRITE_MEM_BARRIER): Define.
* config/cpu/powerpc/atomic_word.h: Likewise.
* config/cpu/sparc/atomic_word.h: Likewise.
* config/cpu/generic/atomic_word.h: Define them, commented out.
* include/bits/atomicity.h: Define defaults.
* config/cpu/ia64/atomic_word.h (__test_and_acquire)
(__set_and_release): New inlines.
(_GLIBCXX_GUARD_TEST_AND_ACQUIRE): Define.
(_GLIBCXX_GUARD_SET_AND_RELEASE): Define.
* libsupc++/guard.cc (acquire_1): Use __builtin_trap instead of
abort();
gcc:
* doc/tm.texi (TARGET_RELAXED_ORDERING): Document.
* target.h (struct gcc_target): Add relaxed_ordering field.
* target-def.h (TARGET_RELAXED_ORDERING): Define default.
(TARGET_INITIALIZER): Add it.
* config/alpha/alpha.c (TARGET_RELAXED_ORDERING): Define.
* config/ia64/ia64.c (TARGET_RELAXED_ORDERING): Define.
* config/rs6000/rs6000.c (TARGET_RELAXED_ORDERING): Define.
* config/sparc/sparc.c (TARGET_RELAXED_ORDERING): Define.
* cp/decl.c (expand_static_init): Don't use shortcut if
targetm.relaxed_ordering.
From-SVN: r92659
This commit is contained in:
Jason Merrill
Jason Merrill
parent
1f7edb8b3d
commit
445cf5eb0d
@ -1,3 +1,14 @@
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2004-12-27 Jason Merrill <jason@redhat.com>
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* doc/tm.texi (TARGET_RELAXED_ORDERING): Document.
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* target.h (struct gcc_target): Add relaxed_ordering field.
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* target-def.h (TARGET_RELAXED_ORDERING): Define default.
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(TARGET_INITIALIZER): Add it.
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* config/alpha/alpha.c (TARGET_RELAXED_ORDERING): Define.
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* config/ia64/ia64.c (TARGET_RELAXED_ORDERING): Define.
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* config/rs6000/rs6000.c (TARGET_RELAXED_ORDERING): Define.
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* config/sparc/sparc.c (TARGET_RELAXED_ORDERING): Define.
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2004-12-27 Roger Sayle <roger@eyesopen.com>
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PR driver/16118
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@ -9462,6 +9462,12 @@ alpha_init_libfuncs (void)
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#undef TARGET_BUILD_BUILTIN_VA_LIST
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#define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
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/* The Alpha architecture does not require sequential consistency. See
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http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html
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for an example of how it can be violated in practice. */
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#undef TARGET_RELAXED_ORDERING
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#define TARGET_RELAXED_ORDERING true
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struct gcc_target targetm = TARGET_INITIALIZER;
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@ -420,6 +420,11 @@ static const struct attribute_spec ia64_attribute_table[] =
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#undef TARGET_SCALAR_MODE_SUPPORTED_P
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#define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
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/* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
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in an order different from the specified program order. */
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#undef TARGET_RELAXED_ORDERING
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#define TARGET_RELAXED_ORDERING true
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struct gcc_target targetm = TARGET_INITIALIZER;
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typedef enum
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@ -1004,6 +1004,17 @@ static const char alt_reg_names[][8] =
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#undef TARGET_VECTOR_MODE_SUPPORTED_P
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#define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
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/* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
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The PowerPC architecture requires only weak consistency among
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processors--that is, memory accesses between processors need not be
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sequentially consistent and memory accesses among processors can occur
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in any order. The ability to order memory accesses weakly provides
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opportunities for more efficient use of the system bus. Unless a
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dependency exists, the 604e allows read operations to precede store
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operations. */
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#undef TARGET_RELAXED_ORDERING
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#define TARGET_RELAXED_ORDERING true
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struct gcc_target targetm = TARGET_INITIALIZER;
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@ -494,6 +494,11 @@ enum processor_type sparc_cpu;
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#define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
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#endif
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/* The SPARC v9 architecture defines a relaxed memory ordering model (RMO)
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which requires this if enabled, though it is never used in userspace,
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and the Ultra3 processors don't implement it. */
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#define TARGET_RELAXED_ORDERING TARGET_V9
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struct gcc_target targetm = TARGET_INITIALIZER;
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/* Validate and override various options, and do some machine dependent
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@ -1,3 +1,8 @@
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2004-12-27 Jason Merrill <jason@redhat.com>
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* decl.c (expand_static_init): Don't use shortcut if
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targetm.relaxed_ordering.
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2004-12-27 Mark Mitchell <mark@codesourcery.com>
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PR c++/19149
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@ -5313,8 +5313,8 @@ expand_static_init (tree decl, tree init)
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if (DECL_FUNCTION_SCOPE_P (decl))
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{
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/* Emit code to perform this initialization but once. */
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tree if_stmt, inner_if_stmt = NULL_TREE;
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tree then_clause, inner_then_clause = NULL_TREE;
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tree if_stmt = NULL_TREE, inner_if_stmt = NULL_TREE;
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tree then_clause = NULL_TREE, inner_then_clause = NULL_TREE;
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tree guard, guard_addr, guard_addr_list;
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tree acquire_fn, release_fn, abort_fn;
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tree flag, begin;
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@ -5353,10 +5353,16 @@ expand_static_init (tree decl, tree init)
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/* Create the guard variable. */
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guard = get_guard (decl);
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/* Begin the conditional initialization. */
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if_stmt = begin_if_stmt ();
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finish_if_stmt_cond (get_guard_cond (guard), if_stmt);
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then_clause = begin_compound_stmt (BCS_NO_SCOPE);
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/* This optimization isn't safe on targets with relaxed memory
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consistency. On such targets we force synchronization in
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__cxa_guard_acquire. */
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if (!targetm.relaxed_ordering || !flag_threadsafe_statics)
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{
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/* Begin the conditional initialization. */
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if_stmt = begin_if_stmt ();
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finish_if_stmt_cond (get_guard_cond (guard), if_stmt);
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then_clause = begin_compound_stmt (BCS_NO_SCOPE);
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}
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if (flag_threadsafe_statics)
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{
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@ -5419,9 +5425,12 @@ expand_static_init (tree decl, tree init)
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finish_if_stmt (inner_if_stmt);
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}
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finish_compound_stmt (then_clause);
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finish_then_clause (if_stmt);
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finish_if_stmt (if_stmt);
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if (!targetm.relaxed_ordering || !flag_threadsafe_statics)
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{
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finish_compound_stmt (then_clause);
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finish_then_clause (if_stmt);
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finish_if_stmt (if_stmt);
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}
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}
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else
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static_aggregates = tree_cons (init, decl, static_aggregates);
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@ -9574,6 +9574,16 @@ If defined, this macro is the number of entries in
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@code{TARGET_FORMAT_TYPES}.
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@end defmac
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@deftypefn {Target Hook} bool TARGET_RELAXED_ORDERING
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If set to @code{true}, means that the target's memory model does not
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guarantee that loads which do not depend on one another will access
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main memory in the order of the instruction stream; if ordering is
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important, an explicit memory barrier must be used. This is true of
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many recent processors which implement a policy of ``relaxed,''
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``weak,'' or ``release'' memory consistency, such as Alpha, PowerPC,
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and ia64. The default is @code{false}.
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@end deftypefn
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@defmac TARGET_USE_JCR_SECTION
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This macro determines whether to use the JCR section to register Java
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classes. By default, TARGET_USE_JCR_SECTION is defined to 1 if both
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@ -394,6 +394,9 @@ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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#define TARGET_GIMPLIFY_VA_ARG_EXPR std_gimplify_va_arg_expr
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#define TARGET_PASS_BY_REFERENCE hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
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#define TARGET_RELAXED_ORDERING false
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#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size_or_pad
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#define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
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@ -533,6 +536,7 @@ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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TARGET_ASM_FILE_START_FILE_DIRECTIVE, \
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TARGET_HANDLE_PRAGMA_REDEFINE_EXTNAME, \
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TARGET_HANDLE_PRAGMA_EXTERN_PREFIX, \
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TARGET_RELAXED_ORDERING, \
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}
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#include "hooks.h"
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@ -598,6 +598,10 @@ struct gcc_target
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/* True if #pragma extern_prefix is to be supported. */
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bool handle_pragma_extern_prefix;
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/* True if the target is allowed to reorder memory accesses unless
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synchronization is explicitly requested. */
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bool relaxed_ordering;
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/* Leave the boolean fields at the end. */
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};
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@ -1,3 +1,31 @@
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2004-12-27 Jason Merrill <jason@redhat.com>
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Add memory barriers to the double-checked locking used for static
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initialization.
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* libsupc++/guard.cc (__test_and_acquire): Define default.
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(_GLIBCXX_GUARD_TEST_AND_ACQUIRE, __set_and_release)
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(_GLIBCXX_GUARD_SET_AND_RELEASE): Likewise.
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(recursion_push, recursion_pop): New abstraction functions.
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(__cxa_guard_acquire): Use _GLIBCXX_GUARD_TEST_AND_ACQUIRE.
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(__cxa_guard_release): Use _GLIBCXX_GUARD_SET_AND_RELEASE.
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* config/cpu/generic/cxxabi_tweaks.h (_GLIBCXX_GUARD_TEST): Rename
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from _GLIBCXX_GUARD_ACQUIRE and reverse sense.
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(_GLIBCXX_GUARD_SET): Rename from _GLIBCXX_GUARD_RELEASE.
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* config/cpu/arm/cxxabi_tweaks.h: Likewise.
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* config/cpu/alpha/atomic_word.h (_GLIBCXX_READ_MEM_BARRIER)
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(_GLIBCXX_WRITE_MEM_BARRIER): Define.
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* config/cpu/powerpc/atomic_word.h: Likewise.
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* config/cpu/sparc/atomic_word.h: Likewise.
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* config/cpu/generic/atomic_word.h: Define them, commented out.
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* include/bits/atomicity.h: Define defaults.
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* config/cpu/ia64/atomic_word.h (__test_and_acquire)
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(__set_and_release): New inlines.
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(_GLIBCXX_GUARD_TEST_AND_ACQUIRE): Define.
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(_GLIBCXX_GUARD_SET_AND_RELEASE): Define.
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* libsupc++/guard.cc (acquire_1): Use __builtin_trap instead of
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abort();
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2004-12-27 Paolo Carlini <pcarlini@suse.de>
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* include/tr1/type_traits: Rework the _DEFINE_SPEC* macros.
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38
libstdc++-v3/config/cpu/alpha/atomic_word.h
Normal file
38
libstdc++-v3/config/cpu/alpha/atomic_word.h
Normal file
@ -0,0 +1,38 @@
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// Low-level type for atomic operations -*- C++ -*-
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// Copyright (C) 2004 Free Software Foundation, Inc.
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//
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// This file is part of the GNU ISO C++ Library. This library is free
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// software; you can redistribute it and/or modify it under the
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// terms of the GNU General Public License as published by the
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// Free Software Foundation; either version 2, or (at your option)
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// any later version.
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// You should have received a copy of the GNU General Public License along
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// with this library; see the file COPYING. If not, write to the Free
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// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
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// USA.
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// As a special exception, you may use this file as part of a free software
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// library without restriction. Specifically, if other files instantiate
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// templates or use macros or inline functions from this file, or you compile
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// this file and link it with other files to produce an executable, this
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// file does not by itself cause the resulting executable to be covered by
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// the GNU General Public License. This exception does not however
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// invalidate any other reasons why the executable file might be covered by
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// the GNU General Public License.
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#ifndef _GLIBCXX_ATOMIC_WORD_H
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#define _GLIBCXX_ATOMIC_WORD_H 1
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typedef int _Atomic_word;
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#define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("mb":::"memory")
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#define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("wmb":::"memory")
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#endif
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@ -38,8 +38,8 @@ namespace __cxxabiv1
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#ifdef __ARM_EABI__
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// The ARM EABI uses the least significant bit of a 32-bit
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// guard variable. */
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#define _GLIBCXX_GUARD_ACQUIRE(x) (!(*(x) & 1))
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#define _GLIBCXX_GUARD_RELEASE(x) *(x) = 1
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#define _GLIBCXX_GUARD_TEST(x) ((*(x) & 1) != 0)
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#define _GLIBCXX_GUARD_SET(x) *(x) = 1
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typedef int __guard;
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// We also want the element size in array cookies.
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@ -54,8 +54,8 @@ namespace __cxxabiv1
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#else // __ARM_EABI__
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// The generic ABI uses the first byte of a 64-bit guard variable.
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#define _GLIBCXX_GUARD_ACQUIRE(x) (!*(char *) (x))
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#define _GLIBCXX_GUARD_RELEASE(x) *(char *) (x) = 1
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#define _GLIBCXX_GUARD_TEST(x) (*(char *) (x) != 0)
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#define _GLIBCXX_GUARD_SET(x) *(char *) (x) = 1
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__extension__ typedef int __guard __attribute__((mode (__DI__)));
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// __cxa_vec_ctor has void return type.
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@ -32,4 +32,17 @@
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typedef int _Atomic_word;
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// Define these two macros using the appropriate memory barrier for the target.
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// The commented out versions below are the defaults.
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// See ia64/atomic_word.h for an alternative approach.
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// This one prevents loads from being hoisted across the barrier;
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// in other words, this is a Load-Load acquire barrier.
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// This is necessary iff TARGET_RELAXED_ORDERING is defined in tm.h.
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// #define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("":::"memory")
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// This one prevents stores from being sunk across the barrier; in other
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// words, a Store-Store release barrier.
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// #define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("":::"memory")
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#endif
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@ -36,8 +36,8 @@ namespace __cxxabiv1
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#endif
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// The generic ABI uses the first byte of a 64-bit guard variable.
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#define _GLIBCXX_GUARD_ACQUIRE(x) (!*(char *) (x))
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#define _GLIBCXX_GUARD_RELEASE(x) *(char *) (x) = 1
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#define _GLIBCXX_GUARD_TEST(x) (*(char *) (x) != 0)
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#define _GLIBCXX_GUARD_SET(x) *(char *) (x) = 1
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__extension__ typedef int __guard __attribute__((mode (__DI__)));
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// __cxa_vec_ctor has void return type.
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69
libstdc++-v3/config/cpu/ia64/atomic_word.h
Normal file
69
libstdc++-v3/config/cpu/ia64/atomic_word.h
Normal file
@ -0,0 +1,69 @@
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// Low-level type for atomic operations -*- C++ -*-
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// Copyright (C) 2004 Free Software Foundation, Inc.
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//
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// This file is part of the GNU ISO C++ Library. This library is free
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// software; you can redistribute it and/or modify it under the
|
||||
// terms of the GNU General Public License as published by the
|
||||
// Free Software Foundation; either version 2, or (at your option)
|
||||
// any later version.
|
||||
|
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// This library is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this library; see the file COPYING. If not, write to the Free
|
||||
// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
|
||||
// USA.
|
||||
|
||||
// As a special exception, you may use this file as part of a free software
|
||||
// library without restriction. Specifically, if other files instantiate
|
||||
// templates or use macros or inline functions from this file, or you compile
|
||||
// this file and link it with other files to produce an executable, this
|
||||
// file does not by itself cause the resulting executable to be covered by
|
||||
// the GNU General Public License. This exception does not however
|
||||
// invalidate any other reasons why the executable file might be covered by
|
||||
// the GNU General Public License.
|
||||
|
||||
#ifndef _GLIBCXX_ATOMIC_WORD_H
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#define _GLIBCXX_ATOMIC_WORD_H 1
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#include <cxxabi.h>
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typedef int _Atomic_word;
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namespace __gnu_cxx
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{
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// Test the first byte of __g and ensure that no loads are hoisted across
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// the test.
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inline bool
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__test_and_acquire (__cxxabiv1::__guard *__g)
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{
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unsigned char __c;
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unsigned char *__p = reinterpret_cast<unsigned char *>(__g);
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// ldN.acq is a load with an implied hoist barrier.
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// would ld8+mask be faster than just doing an ld1?
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__asm __volatile ("ld1.acq %0 = %1" : "=r"(__c) : "m"(*__p) : "memory");
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return __c != 0;
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}
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// Set the first byte of __g to 1 and ensure that no stores are sunk
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// across the store.
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inline void
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__set_and_release (__cxxabiv1::__guard *__g)
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{
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unsigned char *__p = reinterpret_cast<unsigned char *>(__g);
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// stN.rel is a store with an implied sink barrier.
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// could load word, set flag, and CAS it back
|
||||
__asm __volatile ("st1.rel %0 = %1" : "=m"(*__p) : "r"(1) : "memory");
|
||||
}
|
||||
|
||||
// We don't define the _BARRIER macros on ia64 because the barriers are
|
||||
// included in the test and set, above.
|
||||
#define _GLIBCXX_GUARD_TEST_AND_ACQUIRE(G) __gnu_cxx::__test_and_acquire (G)
|
||||
#define _GLIBCXX_GUARD_SET_AND_RELEASE(G) __gnu_cxx::__set_and_release (G)
|
||||
}
|
||||
|
||||
#endif
|
||||
38
libstdc++-v3/config/cpu/powerpc/atomic_word.h
Normal file
38
libstdc++-v3/config/cpu/powerpc/atomic_word.h
Normal file
@ -0,0 +1,38 @@
|
||||
// Low-level type for atomic operations -*- C++ -*-
|
||||
|
||||
// Copyright (C) 2004 Free Software Foundation, Inc.
|
||||
//
|
||||
// This file is part of the GNU ISO C++ Library. This library is free
|
||||
// software; you can redistribute it and/or modify it under the
|
||||
// terms of the GNU General Public License as published by the
|
||||
// Free Software Foundation; either version 2, or (at your option)
|
||||
// any later version.
|
||||
|
||||
// This library is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this library; see the file COPYING. If not, write to the Free
|
||||
// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
|
||||
// USA.
|
||||
|
||||
// As a special exception, you may use this file as part of a free software
|
||||
// library without restriction. Specifically, if other files instantiate
|
||||
// templates or use macros or inline functions from this file, or you compile
|
||||
// this file and link it with other files to produce an executable, this
|
||||
// file does not by itself cause the resulting executable to be covered by
|
||||
// the GNU General Public License. This exception does not however
|
||||
// invalidate any other reasons why the executable file might be covered by
|
||||
// the GNU General Public License.
|
||||
|
||||
#ifndef _GLIBCXX_ATOMIC_WORD_H
|
||||
#define _GLIBCXX_ATOMIC_WORD_H 1
|
||||
|
||||
typedef int _Atomic_word;
|
||||
|
||||
#define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("isync":::"memory")
|
||||
#define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
|
||||
|
||||
#endif
|
||||
@ -36,4 +36,18 @@
|
||||
typedef int _Atomic_word;
|
||||
#endif
|
||||
|
||||
#if defined(__sparc_v9__)
|
||||
// These are necessary under the V9 RMO model, though it is almost never
|
||||
// used in userspace.
|
||||
#define _GLIBCXX_READ_MEM_BARRIER \
|
||||
__asm __volatile ("membar #LoadLoad":::"memory")
|
||||
#define _GLIBCXX_WRITE_MEM_BARRIER \
|
||||
__asm __volatile ("membar #StoreStore":::"memory")
|
||||
|
||||
#elif defined(__sparc_v8__)
|
||||
// This is necessary under the PSO model.
|
||||
#define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("stbar":::"memory")
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -48,4 +48,13 @@ namespace __gnu_cxx
|
||||
__atomic_add(volatile _Atomic_word* __mem, int __val);
|
||||
} // namespace __gnu_cxx
|
||||
|
||||
/* Even if the CPU doesn't need a memory barrier, we need to ensure that
|
||||
the compiler doesn't reorder memory accesses across the barriers. */
|
||||
#ifndef _GLIBCXX_READ_MEM_BARRIER
|
||||
#define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("":::"memory")
|
||||
#endif
|
||||
#ifndef _GLIBCXX_WRITE_MEM_BARRIER
|
||||
#define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("":::"memory")
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -27,11 +27,13 @@
|
||||
// the GNU General Public License.
|
||||
|
||||
// Written by Mark Mitchell, CodeSourcery LLC, <mark@codesourcery.com>
|
||||
// Thread support written by Jason Merrill, Red Hat Inc. <jason@redhat.com>
|
||||
|
||||
#include <cxxabi.h>
|
||||
#include <exception>
|
||||
#include <bits/c++config.h>
|
||||
#include <bits/gthr.h>
|
||||
#include <bits/atomicity.h>
|
||||
|
||||
// The IA64/generic ABI uses the first byte of the guard variable.
|
||||
// The ARM EABI uses the least significant bit.
|
||||
@ -84,8 +86,36 @@ namespace
|
||||
__gthread_recursive_mutex_unlock (&mutex);
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef _GLIBCXX_GUARD_TEST_AND_ACQUIRE
|
||||
inline bool
|
||||
__test_and_acquire (__cxxabiv1::__guard *g)
|
||||
{
|
||||
bool b = _GLIBCXX_GUARD_TEST (g);
|
||||
_GLIBCXX_READ_MEM_BARRIER;
|
||||
return b;
|
||||
}
|
||||
#define _GLIBCXX_GUARD_TEST_AND_ACQUIRE(G) __test_and_acquire (G)
|
||||
#endif
|
||||
|
||||
#ifndef _GLIBCXX_GUARD_SET_AND_RELEASE
|
||||
inline void
|
||||
__set_and_release (__cxxabiv1::__guard *g)
|
||||
{
|
||||
_GLIBCXX_WRITE_MEM_BARRIER;
|
||||
_GLIBCXX_GUARD_SET (g);
|
||||
}
|
||||
#define _GLIBCXX_GUARD_SET_AND_RELEASE(G) __set_and_release (G)
|
||||
#endif
|
||||
|
||||
#else /* !__GTHREADS */
|
||||
|
||||
#undef _GLIBCXX_GUARD_TEST_AND_ACQUIRE
|
||||
#undef _GLIBCXX_GUARD_SET_AND_RELEASE
|
||||
#define _GLIBCXX_GUARD_SET_AND_RELEASE(G) _GLIBCXX_GUARD_SET (G)
|
||||
|
||||
#endif /* __GTHREADS */
|
||||
|
||||
namespace __gnu_cxx
|
||||
{
|
||||
// 6.7[stmt.dcl]/4: If control re-enters the declaration (recursively)
|
||||
@ -107,28 +137,46 @@ namespace __gnu_cxx
|
||||
|
||||
namespace __cxxabiv1
|
||||
{
|
||||
static inline int
|
||||
recursion_push (__guard* g)
|
||||
{
|
||||
return ((char *)g)[1]++;
|
||||
}
|
||||
|
||||
static inline void
|
||||
recursion_pop (__guard* g)
|
||||
{
|
||||
--((char *)g)[1];
|
||||
}
|
||||
|
||||
static int
|
||||
acquire_1 (__guard *g)
|
||||
{
|
||||
if (_GLIBCXX_GUARD_ACQUIRE (g))
|
||||
if (_GLIBCXX_GUARD_TEST (g))
|
||||
return 0;
|
||||
|
||||
if (recursion_push (g))
|
||||
{
|
||||
if (((char *)g)[1]++)
|
||||
{
|
||||
#ifdef __EXCEPTIONS
|
||||
throw __gnu_cxx::recursive_init();
|
||||
throw __gnu_cxx::recursive_init();
|
||||
#else
|
||||
abort ();
|
||||
// Use __builtin_trap so we don't require abort().
|
||||
__builtin_trap ();
|
||||
#endif
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
extern "C"
|
||||
int __cxa_guard_acquire (__guard *g)
|
||||
{
|
||||
#ifdef __GTHREADS
|
||||
// If the target can reorder loads, we need to insert a read memory
|
||||
// barrier so that accesses to the guarded variable happen after the
|
||||
// guard test.
|
||||
if (_GLIBCXX_GUARD_TEST_AND_ACQUIRE (g))
|
||||
return 0;
|
||||
|
||||
if (__gthread_active_p ())
|
||||
{
|
||||
// Simple wrapper for exception safety.
|
||||
@ -162,7 +210,7 @@ namespace __cxxabiv1
|
||||
extern "C"
|
||||
void __cxa_guard_abort (__guard *g)
|
||||
{
|
||||
((char *)g)[1]--;
|
||||
recursion_pop (g);
|
||||
#ifdef __GTHREADS
|
||||
if (__gthread_active_p ())
|
||||
static_mutex::unlock ();
|
||||
@ -172,8 +220,8 @@ namespace __cxxabiv1
|
||||
extern "C"
|
||||
void __cxa_guard_release (__guard *g)
|
||||
{
|
||||
((char *)g)[1]--;
|
||||
_GLIBCXX_GUARD_RELEASE (g);
|
||||
recursion_pop (g);
|
||||
_GLIBCXX_GUARD_SET_AND_RELEASE (g);
|
||||
#ifdef __GTHREADS
|
||||
if (__gthread_active_p ())
|
||||
static_mutex::unlock ();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user