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* common/config/i386/i386-common.c (OPTION_MASK_ISA_PREFETCHWT1_SET), (OPTION_MASK_ISA_PREFETCHWT1_UNSET): New. (ix86_handle_option): Handle OPT_mprefetchwt1. * config/i386/cpuid.h (bit_PREFETCHWT1): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect PREFETCHWT1 CPUID. * config/i386/i386-c.c (ix86_target_macros_internal): Handle OPTION_MASK_ISA_PREFETCHWT1. * config/i386/i386.c (ix86_target_string): Handle mprefetchwt1. (PTA_PREFETCHWT1): New. (ix86_option_override_internal): Handle PTA_PREFETCHWT1. (ix86_valid_target_attribute_inner_p): Handle OPT_mprefetchwt1. * config/i386/i386.h (TARGET_PREFETCHWT1), (TARGET_PREFETCHWT1_P): New. * config/i386/i386.md (prefetch): Check TARGET_PREFETCHWT1 (*prefetch_avx512pf_<mode>_: Change into ... (*prefetch_prefetchwt1_<mode>: This. * config/i386/i386.opt (mprefetchwt1): New. * config/i386/xmmintrin.h (_mm_hint): Add _MM_HINT_ET1. (_mm_prefetch): Handle intent to write. * doc/invoke.texi (mprefetchwt1), (mno-prefetchwt1): Doccument. gcc/testsuite/ * gcc.target/i386/avx-1.c: Update __builtin_prefetch. * gcc.target/i386/prefetchwt1-1.c: New. * g++.dg/other/i386-2.C: Add new option. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Update __builtin_prefetch, add new option. * gcc.target/i386/sse-22.c: Add new option. * gcc.target/i386/sse-23.c: Update __builtin_prefetch, add new option. From-SVN: r208115
This commit is contained in:
Ilya Tocar
Kirill Yukhin
parent
a51524153c
commit
43b3f52f4a
@ -1,3 +1,27 @@
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2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
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* common/config/i386/i386-common.c (OPTION_MASK_ISA_PREFETCHWT1_SET),
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(OPTION_MASK_ISA_PREFETCHWT1_UNSET): New.
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(ix86_handle_option): Handle OPT_mprefetchwt1.
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* config/i386/cpuid.h (bit_PREFETCHWT1): New.
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* config/i386/driver-i386.c (host_detect_local_cpu): Detect
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PREFETCHWT1 CPUID.
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* config/i386/i386-c.c (ix86_target_macros_internal): Handle
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OPTION_MASK_ISA_PREFETCHWT1.
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* config/i386/i386.c (ix86_target_string): Handle mprefetchwt1.
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(PTA_PREFETCHWT1): New.
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(ix86_option_override_internal): Handle PTA_PREFETCHWT1.
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(ix86_valid_target_attribute_inner_p): Handle OPT_mprefetchwt1.
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* config/i386/i386.h (TARGET_PREFETCHWT1), (TARGET_PREFETCHWT1_P):
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New.
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* config/i386/i386.md (prefetch): Check TARGET_PREFETCHWT1
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(*prefetch_avx512pf_<mode>_: Change into ...
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(*prefetch_prefetchwt1_<mode>: This.
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* config/i386/i386.opt (mprefetchwt1): New.
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* config/i386/xmmintrin.h (_mm_hint): Add _MM_HINT_ET1.
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(_mm_prefetch): Handle intent to write.
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* doc/invoke.texi (mprefetchwt1), (mno-prefetchwt1): Doccument.
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2014-02-25 Richard Biener <rguenther@suse.de>
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PR middle-end/60291
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@ -17,7 +41,7 @@
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(run_gcc): And pass them through.
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2014-02-25 Andrey Belevantsev <abel@ispras.ru>
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* sel-sched.c (calculate_new_fences): New parameter ptime.
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Calculate it as a maximum over all fence cycles.
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(sel_sched_region_2): Adjust the call to calculate_new_fences.
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@ -69,6 +69,7 @@ along with GCC; see the file COPYING3. If not see
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#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
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#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
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#define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
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#define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
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/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
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as -msse4.2. */
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@ -154,6 +155,7 @@ along with GCC; see the file COPYING3. If not see
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#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
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#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
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#define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
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#define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
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/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
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as -mno-sse4.1. */
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@ -757,6 +759,19 @@ ix86_handle_option (struct gcc_options *opts,
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}
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return true;
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case OPT_mprefetchwt1:
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if (value)
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{
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET;
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opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET;
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}
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else
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{
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opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET;
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opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET;
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}
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return true;
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/* Comes from final.c -- no real reason to change it. */
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#define MAX_CODE_ALIGN 16
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@ -65,6 +65,7 @@
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#define bit_3DNOW (1 << 31)
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/* Extended Features (%eax == 7) */
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/* %ebx */
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#define bit_FSGSBASE (1 << 0)
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#define bit_BMI (1 << 3)
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#define bit_HLE (1 << 4)
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@ -79,6 +80,9 @@
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#define bit_AVX512CD (1 << 28)
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#define bit_SHA (1 << 29)
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/* %ecx */
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#define bit_PREFETCHWT1 (1 << 0)
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/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
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#define bit_XSAVEOPT (1 << 0)
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@ -409,7 +409,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
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unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
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unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
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unsigned int has_avx512f = 0, has_sha = 0;
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unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
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bool arch;
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@ -486,6 +486,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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has_avx512pf = ebx & bit_AVX512PF;
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has_avx512cd = ebx & bit_AVX512CD;
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has_sha = ebx & bit_SHA;
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has_prefetchwt1 = ecx & bit_PREFETCHWT1;
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}
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if (max_level >= 13)
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@ -883,6 +885,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
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const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
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const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
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const char *prefetchwt1 = has_prefetchwt1 ? " -mprefetchwt1" : " -mno-prefetchwt1";
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options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
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sse4a, cx16, sahf, movbe, aes, sha, pclmul,
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@ -890,7 +893,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
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hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
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fxsr, xsave, xsaveopt, avx512f, avx512er,
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avx512cd, avx512pf, NULL);
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avx512cd, avx512pf, prefetchwt1, NULL);
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}
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done:
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@ -387,6 +387,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__XSAVE__");
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if (isa_flag & OPTION_MASK_ISA_XSAVEOPT)
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def_or_undef (parse_in, "__XSAVEOPT__");
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if (isa_flag & OPTION_MASK_ISA_PREFETCHWT1)
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def_or_undef (parse_in, "__PREFETCHWT1__");
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if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE))
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def_or_undef (parse_in, "__SSE_MATH__");
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if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE2))
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@ -2622,6 +2622,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
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{ "-mrtm", OPTION_MASK_ISA_RTM },
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{ "-mxsave", OPTION_MASK_ISA_XSAVE },
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{ "-mxsaveopt", OPTION_MASK_ISA_XSAVEOPT },
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{ "-mprefetchwt1", OPTION_MASK_ISA_PREFETCHWT1 },
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};
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/* Flag options. */
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@ -3112,6 +3113,7 @@ ix86_option_override_internal (bool main_args_p,
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#define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
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#define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
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#define PTA_SHA (HOST_WIDE_INT_1 << 45)
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#define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
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#define PTA_CORE2 \
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(PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
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@ -3666,6 +3668,9 @@ ix86_option_override_internal (bool main_args_p,
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if (processor_alias_table[i].flags & PTA_AVX512CD
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&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512CD))
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD;
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if (processor_alias_table[i].flags & PTA_PREFETCHWT1
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&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PREFETCHWT1))
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opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1;
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if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
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x86_prefetch_sse = true;
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@ -4547,6 +4552,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
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IX86_ATTR_ISA ("fxsr", OPT_mfxsr),
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IX86_ATTR_ISA ("xsave", OPT_mxsave),
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IX86_ATTR_ISA ("xsaveopt", OPT_mxsaveopt),
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IX86_ATTR_ISA ("prefetchwt1", OPT_mprefetchwt1),
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/* enum options */
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IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
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@ -130,6 +130,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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#define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x)
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#define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT
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#define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x)
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#define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1
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#define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x)
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#define TARGET_LP64 TARGET_ABI_64
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#define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
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@ -17856,7 +17856,7 @@
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[(prefetch (match_operand 0 "address_operand")
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(match_operand:SI 1 "const_int_operand")
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(match_operand:SI 2 "const_int_operand"))]
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"TARGET_PREFETCH_SSE || TARGET_PRFCHW || TARGET_AVX512PF"
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"TARGET_PREFETCH_SSE || TARGET_PRFCHW || TARGET_PREFETCHWT1"
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{
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bool write = INTVAL (operands[1]) != 0;
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int locality = INTVAL (operands[2]);
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@ -17867,8 +17867,8 @@
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supported by SSE counterpart or the SSE prefetch is not available
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(K6 machines). Otherwise use SSE prefetch as it allows specifying
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of locality. */
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if (TARGET_AVX512PF && write)
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operands[2] = const1_rtx;
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if (TARGET_PREFETCHWT1 && write)
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operands[2] = const2_rtx;
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else if (TARGET_PRFCHW && (write || !TARGET_PREFETCH_SSE))
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operands[2] = GEN_INT (3);
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else
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@ -17912,14 +17912,13 @@
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(symbol_ref "memory_address_length (operands[0], false)"))
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(set_attr "memory" "none")])
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(define_insn "*prefetch_avx512pf_<mode>"
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(define_insn "*prefetch_prefetchwt1_<mode>"
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[(prefetch (match_operand:P 0 "address_operand" "p")
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(const_int 1)
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(const_int 1))]
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"TARGET_AVX512PF"
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(const_int 2))]
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"TARGET_PREFETCHWT1"
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"prefetchwt1\t%a0";
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[(set_attr "type" "sse")
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(set_attr "prefix" "evex")
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(set (attr "length_address")
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(symbol_ref "memory_address_length (operands[0], false)"))
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(set_attr "memory" "none")])
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@ -757,6 +757,10 @@ mf16c
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Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
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Support F16C built-in functions and code generation
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mprefetchwt1
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Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save
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Support PREFETCHWT1 built-in functions and code generation
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mfentry
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Target Report Var(flag_fentry) Init(-1)
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Emit profiling counter call at function entry before prologue.
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@ -53,6 +53,8 @@ typedef float __v4sf __attribute__ ((__vector_size__ (16)));
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/* Constants for use with _mm_prefetch. */
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enum _mm_hint
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{
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/* _MM_HINT_ET is _MM_HINT_T with set 3rd bit. */
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_MM_HINT_ET1 = 6,
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_MM_HINT_T0 = 3,
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_MM_HINT_T1 = 2,
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_MM_HINT_T2 = 1,
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@ -1191,11 +1193,11 @@ _m_psadbw (__m64 __A, __m64 __B)
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extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_prefetch (const void *__P, enum _mm_hint __I)
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{
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__builtin_prefetch (__P, 0, __I);
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__builtin_prefetch (__P, (__I & 0x4) >> 2, __I & 0x3);
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}
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#else
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#define _mm_prefetch(P, I) \
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__builtin_prefetch ((P), 0, (I))
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__builtin_prefetch ((P), ((I & 0x4) >> 2), (I & 0x3))
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#endif
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/* Stores the data in A to the address P without polluting the caches. */
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@ -667,7 +667,7 @@ Objective-C and Objective-C++ Dialects}.
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-mvzeroupper -mprefer-avx128 @gol
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-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
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-mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd -msha @gol
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-maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol
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-maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma -mprefetchwt1 @gol
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-msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol
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-mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp -mthreads @gol
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-mno-align-stringops -minline-all-stringops @gol
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@ -15265,6 +15265,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
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@itemx -mno-f16c
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@itemx -mfma
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@itemx -mno-fma
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@itemx -mprefetchwt1
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@itemx -mno-prefetchwt1
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@itemx -msse4a
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@itemx -mno-sse4a
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@itemx -mfma4
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@ -1,3 +1,14 @@
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2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
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* gcc.target/i386/avx-1.c: Update __builtin_prefetch.
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* gcc.target/i386/prefetchwt1-1.c: New.
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* g++.dg/other/i386-2.C: Add new option.
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* g++.dg/other/i386-3.C: Ditto.
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* gcc.target/i386/sse-12.c: Ditto.
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* gcc.target/i386/sse-13.c: Update __builtin_prefetch, add new option.
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* gcc.target/i386/sse-22.c: Add new option.
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* gcc.target/i386/sse-23.c: Update __builtin_prefetch, add new option.
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2014-02-25 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
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PR libfortran/59313
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@ -1,5 +1,5 @@
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/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
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/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha" } */
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/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1" } */
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/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
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xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
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@ -1,5 +1,5 @@
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/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
|
||||
/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha" } */
|
||||
/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1" } */
|
||||
|
||||
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
|
||||
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
|
||||
|
||||
@ -152,7 +152,7 @@
|
||||
#define __builtin_ia32_shufpd(A, B, N) __builtin_ia32_shufpd(A, B, 0)
|
||||
|
||||
/* xmmintrin.h */
|
||||
#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, A, _MM_HINT_NTA)
|
||||
#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, 0, _MM_HINT_NTA)
|
||||
#define __builtin_ia32_pshufw(A, N) __builtin_ia32_pshufw(A, 0)
|
||||
#define __builtin_ia32_vec_set_v4hi(A, D, N) \
|
||||
__builtin_ia32_vec_set_v4hi(A, D, 0)
|
||||
|
||||
14
gcc/testsuite/gcc.target/i386/prefetchwt1-1.c
Normal file
14
gcc/testsuite/gcc.target/i386/prefetchwt1-1.c
Normal file
@ -0,0 +1,14 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mprefetchwt1 -O2" } */
|
||||
/* { dg-final { scan-assembler "\[ \\t\]+prefetchwt1\[ \\t\]+" } } */
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
||||
void *p;
|
||||
|
||||
void extern
|
||||
prefetchw__test (void)
|
||||
{
|
||||
_mm_prefetch (p, _MM_HINT_ET1);
|
||||
}
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
popcntintrin.h and mm_malloc.h are usable
|
||||
with -O -std=c89 -pedantic-errors. */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha" } */
|
||||
/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1" } */
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha" } */
|
||||
/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1" } */
|
||||
|
||||
#include <mm_malloc.h>
|
||||
|
||||
@ -138,7 +138,7 @@
|
||||
#define __builtin_ia32_shufpd(A, B, N) __builtin_ia32_shufpd(A, B, 0)
|
||||
|
||||
/* xmmintrin.h */
|
||||
#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, A, _MM_HINT_NTA)
|
||||
#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, 0, _MM_HINT_NTA)
|
||||
#define __builtin_ia32_pshufw(A, N) __builtin_ia32_pshufw(A, 0)
|
||||
#define __builtin_ia32_vec_set_v4hi(A, D, N) \
|
||||
__builtin_ia32_vec_set_v4hi(A, D, 0)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha" } */
|
||||
/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1" } */
|
||||
|
||||
#include <mm_malloc.h>
|
||||
|
||||
|
||||
@ -99,7 +99,7 @@
|
||||
|
||||
|
||||
#ifndef DIFFERENT_PRAGMAS
|
||||
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha")
|
||||
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1")
|
||||
#endif
|
||||
|
||||
/* Following intrinsics require immediate arguments. They
|
||||
|
||||
@ -90,7 +90,7 @@
|
||||
#define __builtin_ia32_shufpd(A, B, N) __builtin_ia32_shufpd(A, B, 0)
|
||||
|
||||
/* xmmintrin.h */
|
||||
#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, A, _MM_HINT_NTA)
|
||||
#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, 0, _MM_HINT_NTA)
|
||||
#define __builtin_ia32_pshufw(A, N) __builtin_ia32_pshufw(A, 0)
|
||||
#define __builtin_ia32_vec_set_v4hi(A, D, N) \
|
||||
__builtin_ia32_vec_set_v4hi(A, D, 0)
|
||||
@ -385,7 +385,7 @@
|
||||
/* shaintrin.h */
|
||||
#define __builtin_ia32_sha1rnds4(A, B, C) __builtin_ia32_sha1rnds4(A, B, 1)
|
||||
|
||||
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha")
|
||||
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1")
|
||||
#include <wmmintrin.h>
|
||||
#include <smmintrin.h>
|
||||
#include <mm3dnow.h>
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user