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AVX-512. Add pd2dq and dq2pd converts.
gcc/ * config/i386/i386.c (avx512f_ufix_notruncv8dfv8si_mask_round): Rename to ... (ufix_notruncv8dfv8si2_mask_round): ... this. * config/i386/sse.md (define_insn "avx512f_cvtdq2pd512_2): Update TARGET check. (define_insn "avx_cvtdq2pd256_2"): Add EVEX version. (define_insn "sse2_cvtdq2pd<mask_name>"): Add masking. (define_insn "avx_cvtpd2dq256<mask_name>"): Ditto. (define_expand "sse2_cvtpd2dq"): Delete. (define_insn "sse2_cvtpd2dq<mask_name>"): Add masking and make 2nd operand const0 vector. (define_insn "avx512f_ufix_notruncv8dfv8si<mask_name><round_name>"): Delete. (define_mode_attr pd2udqsuff): New. (define_insn "ufix_notrunc<mode><si2dfmodelower>2<mask_name><round_name>"): Ditto. (define_insn "ufix_notruncv2dfv2si2<mask_name>"): Ditto. (define_insn "*avx_cvttpd2dq256_2"): Delete. (define_expand "sse2_cvttpd2dq"): Ditto. (define_insn "sse2_cvttpd2dq<mask_name>"): Add masking and make 2nd operand const0 vector. Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com> Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com> Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com> Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com> Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com> Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com> Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com> From-SVN: r215584
This commit is contained in:
Alexander Ivchenko
Kirill Yukhin
parent
356bbc4c20
commit
42815c486a
@ -1,3 +1,34 @@
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2014-09-25 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* config/i386/i386.c
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(avx512f_ufix_notruncv8dfv8si_mask_round): Rename to ...
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(ufix_notruncv8dfv8si2_mask_round): ... this.
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* config/i386/sse.md
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(define_insn "avx512f_cvtdq2pd512_2): Update TARGET check.
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(define_insn "avx_cvtdq2pd256_2"): Add EVEX version.
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(define_insn "sse2_cvtdq2pd<mask_name>"): Add masking.
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(define_insn "avx_cvtpd2dq256<mask_name>"): Ditto.
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(define_expand "sse2_cvtpd2dq"): Delete.
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(define_insn "sse2_cvtpd2dq<mask_name>"): Add masking and
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make 2nd operand const0 vector.
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(define_insn "avx512f_ufix_notruncv8dfv8si<mask_name><round_name>"):
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Delete.
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(define_mode_attr pd2udqsuff): New.
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(define_insn
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"ufix_notrunc<mode><si2dfmodelower>2<mask_name><round_name>"): Ditto.
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(define_insn "ufix_notruncv2dfv2si2<mask_name>"): Ditto.
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(define_insn "*avx_cvttpd2dq256_2"): Delete.
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(define_expand "sse2_cvttpd2dq"): Ditto.
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(define_insn "sse2_cvttpd2dq<mask_name>"): Add masking and
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make 2nd operand const0 vector.
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2014-09-25 Jakub Jelinek <jakub@redhat.com>
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PR tree-optimization/63341
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@ -30246,7 +30246,7 @@ static const struct builtin_description bdesc_round_args[] =
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{ OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
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{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
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{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
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{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
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{ OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
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{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
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{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
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{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
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@ -4463,33 +4463,33 @@
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(const_int 2) (const_int 3)
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(const_int 4) (const_int 5)
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(const_int 6) (const_int 7)]))))]
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"TARGET_AVX"
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"TARGET_AVX512F"
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"vcvtdq2pd\t{%t1, %0|%0, %t1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "V8DF")])
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(define_insn "avx_cvtdq2pd256_2"
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[(set (match_operand:V4DF 0 "register_operand" "=x")
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[(set (match_operand:V4DF 0 "register_operand" "=v")
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(float:V4DF
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(vec_select:V4SI
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(match_operand:V8SI 1 "nonimmediate_operand" "xm")
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(match_operand:V8SI 1 "nonimmediate_operand" "vm")
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)]))))]
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"TARGET_AVX"
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"vcvtdq2pd\t{%x1, %0|%0, %x1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "vex")
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(set_attr "prefix" "maybe_evex")
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(set_attr "mode" "V4DF")])
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(define_insn "sse2_cvtdq2pd"
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[(set (match_operand:V2DF 0 "register_operand" "=x")
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(define_insn "sse2_cvtdq2pd<mask_name>"
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[(set (match_operand:V2DF 0 "register_operand" "=v")
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(float:V2DF
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(vec_select:V2SI
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(match_operand:V4SI 1 "nonimmediate_operand" "xm")
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(match_operand:V4SI 1 "nonimmediate_operand" "vm")
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(parallel [(const_int 0) (const_int 1)]))))]
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"TARGET_SSE2"
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"%vcvtdq2pd\t{%1, %0|%0, %q1}"
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"TARGET_SSE2 && <mask_avx512vl_condition>"
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"%vcvtdq2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "maybe_vex")
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(set_attr "ssememalign" "64")
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@ -4506,14 +4506,14 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "OI")])
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(define_insn "avx_cvtpd2dq256"
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[(set (match_operand:V4SI 0 "register_operand" "=x")
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(unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "xm")]
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(define_insn "avx_cvtpd2dq256<mask_name>"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "vm")]
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UNSPEC_FIX_NOTRUNC))]
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"TARGET_AVX"
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"vcvtpd2dq{y}\t{%1, %0|%0, %1}"
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"TARGET_AVX && <mask_avx512vl_condition>"
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"vcvtpd2dq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "vex")
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(set_attr "prefix" "<mask_prefix>")
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(set_attr "mode" "OI")])
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(define_expand "avx_cvtpd2dq256_2"
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@ -4538,25 +4538,16 @@
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(set_attr "btver2_decode" "vector")
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(set_attr "mode" "OI")])
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(define_expand "sse2_cvtpd2dq"
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[(set (match_operand:V4SI 0 "register_operand")
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(define_insn "sse2_cvtpd2dq<mask_name>"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(vec_concat:V4SI
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(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand")]
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(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "vm")]
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UNSPEC_FIX_NOTRUNC)
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(match_dup 2)))]
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"TARGET_SSE2"
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"operands[2] = CONST0_RTX (V2SImode);")
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(define_insn "*sse2_cvtpd2dq"
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[(set (match_operand:V4SI 0 "register_operand" "=x")
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(vec_concat:V4SI
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(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
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UNSPEC_FIX_NOTRUNC)
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(match_operand:V2SI 2 "const0_operand")))]
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"TARGET_SSE2"
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(const_vector:V2SI [(const_int 0) (const_int 0)])))]
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"TARGET_SSE2 && <mask_avx512vl_condition>"
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{
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if (TARGET_AVX)
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return "vcvtpd2dq{x}\t{%1, %0|%0, %1}";
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return "vcvtpd2dq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}";
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else
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return "cvtpd2dq\t{%1, %0|%0, %1}";
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}
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@ -4569,16 +4560,33 @@
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(set_attr "athlon_decode" "vector")
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(set_attr "bdver1_decode" "double")])
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(define_insn "avx512f_ufix_notruncv8dfv8si<mask_name><round_name>"
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[(set (match_operand:V8SI 0 "register_operand" "=v")
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(unspec:V8SI
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[(match_operand:V8DF 1 "<round_nimm_predicate>" "<round_constraint>")]
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;; For ufix_notrunc* insn patterns
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(define_mode_attr pd2udqsuff
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[(V8DF "") (V4DF "{y}")])
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(define_insn "ufix_notrunc<mode><si2dfmodelower>2<mask_name><round_name>"
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[(set (match_operand:<si2dfmode> 0 "register_operand" "=v")
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(unspec:<si2dfmode>
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[(match_operand:VF2_512_256VL 1 "nonimmediate_operand" "<round_constraint>")]
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UNSPEC_UNSIGNED_FIX_NOTRUNC))]
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"TARGET_AVX512F"
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"vcvtpd2udq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
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"vcvtpd2udq<pd2udqsuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "OI")])
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "ufix_notruncv2dfv2si2<mask_name>"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(vec_concat:V4SI
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(unspec:V2SI
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[(match_operand:V2DF 1 "nonimmediate_operand" "vm")]
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UNSPEC_UNSIGNED_FIX_NOTRUNC)
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(const_vector:V2SI [(const_int 0) (const_int 0)])))]
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"TARGET_AVX512VL"
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"vcvtpd2udq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "TI")])
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(define_insn "<fixsuffix>fix_truncv8dfv8si2<mask_name><round_saeonly_name>"
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[(set (match_operand:V8SI 0 "register_operand" "=v")
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@ -4659,35 +4667,15 @@
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"TARGET_AVX"
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"operands[2] = CONST0_RTX (V4SImode);")
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(define_insn "*avx_cvttpd2dq256_2"
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[(set (match_operand:V8SI 0 "register_operand" "=x")
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(vec_concat:V8SI
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(fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "xm"))
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(match_operand:V4SI 2 "const0_operand")))]
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"TARGET_AVX"
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"vcvttpd2dq{y}\t{%1, %x0|%x0, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "vex")
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(set_attr "btver2_decode" "vector")
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(set_attr "mode" "OI")])
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(define_expand "sse2_cvttpd2dq"
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[(set (match_operand:V4SI 0 "register_operand")
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(define_insn "sse2_cvttpd2dq<mask_name>"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(vec_concat:V4SI
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(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand"))
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(match_dup 2)))]
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"TARGET_SSE2"
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"operands[2] = CONST0_RTX (V2SImode);")
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(define_insn "*sse2_cvttpd2dq"
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[(set (match_operand:V4SI 0 "register_operand" "=x")
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(vec_concat:V4SI
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(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
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(match_operand:V2SI 2 "const0_operand")))]
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"TARGET_SSE2"
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(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vm"))
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(const_vector:V2SI [(const_int 0) (const_int 0)])))]
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"TARGET_SSE2 && <mask_avx512vl_condition>"
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{
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if (TARGET_AVX)
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return "vcvttpd2dq{x}\t{%1, %0|%0, %1}";
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return "vcvttpd2dq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}";
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else
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return "cvttpd2dq\t{%1, %0|%0, %1}";
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}
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