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mips.c (PROCESSOR_R4320, [...]): Remove.
* config/mips/mips.c (PROCESSOR_R4320, TARGET_MIPS4320): Remove. (GENERATE_MULT3_SI): Remove use of TARGET_MIPS4320. * config/mips/mips.c (mips_cpu_info): Remove vr4320 entry. * config/mips/mips.md (define_attr cpu): Remove r4320. Remove vr4320 scheduler and uses of TARGET_MIPS4320. From-SVN: r57686
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
366356d3e6
commit
41f9efba65
@ -1,3 +1,11 @@
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2002-10-01 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.c (PROCESSOR_R4320, TARGET_MIPS4320): Remove.
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(GENERATE_MULT3_SI): Remove use of TARGET_MIPS4320.
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* config/mips/mips.c (mips_cpu_info): Remove vr4320 entry.
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* config/mips/mips.md (define_attr cpu): Remove r4320.
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Remove vr4320 scheduler and uses of TARGET_MIPS4320.
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2002-10-01 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.c (mips16_strings): New variable.
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@ -598,7 +598,6 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
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{ "vr4111", PROCESSOR_R4111, 3 },
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{ "vr4121", PROCESSOR_R4121, 3 },
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{ "vr4300", PROCESSOR_R4300, 3 },
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{ "vr4320", PROCESSOR_R4320, 3 },
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{ "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
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{ "r4600", PROCESSOR_R4600, 3 },
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{ "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
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@ -66,7 +66,6 @@ enum processor_type {
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PROCESSOR_R4111,
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PROCESSOR_R4121,
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PROCESSOR_R4300,
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PROCESSOR_R4320,
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PROCESSOR_R4600,
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PROCESSOR_R4650,
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PROCESSOR_R5000,
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@ -360,7 +359,6 @@ extern void sbss_section PARAMS ((void));
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#define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
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#define TARGET_MIPS4121 (mips_arch == PROCESSOR_R4121)
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#define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
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#define TARGET_MIPS4320 (mips_arch == PROCESSOR_R4320)
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#define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
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#define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
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#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
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@ -769,7 +767,6 @@ extern void sbss_section PARAMS ((void));
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/* Generate three-operand multiply instructions for SImode. */
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#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
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|| TARGET_MIPS4320 \
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|| TARGET_MIPS5400 \
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|| TARGET_MIPS5500 \
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|| ISA_MIPS32 \
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@ -122,7 +122,7 @@
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;; ??? Fix everything that tests this attribute.
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(define_attr "cpu"
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"default,r3000,r3900,r6000,r4000,r4100,r4121,r4300,r4320,r4600,r4650,r5000,r5400,r5500,r8000,sr71000,r4kc,r5kc,r20kc"
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"default,r3000,r3900,r6000,r4000,r4100,r4121,r4300,r4600,r4650,r5000,r5400,r5500,r8000,sr71000,r4kc,r5kc,r20kc"
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(const (symbol_ref "mips_cpu_attr")))
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;; Does the instruction have a mandatory delay slot?
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@ -207,12 +207,12 @@
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(define_function_unit "memory" 1 0
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(and (eq_attr "type" "load")
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(eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4121,r4300,r4320,r5000"))
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(eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4121,r4300,r5000"))
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3 0)
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(define_function_unit "memory" 1 0
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(and (eq_attr "type" "load")
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(eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4121,r4300,r4320,r5000"))
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(eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4121,r4300,r5000"))
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2 0)
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(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
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@ -225,7 +225,7 @@
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "imul,imadd")
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(eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4121,r4300,r4320,r5000"))
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(eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4121,r4300,r5000"))
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17 17)
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;; On them mips16, we want to stronly discourage a mult from appearing
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@ -262,12 +262,12 @@
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "imul,imadd")
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(and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r4320,r5000")))
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(and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000")))
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5 5)
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "imul,imadd")
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(and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300,r4320")))
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(and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
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8 8)
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(define_function_unit "imuldiv" 1 0
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@ -277,7 +277,7 @@
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4121,r4300,r4320,r5000"))
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(eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4121,r4300,r5000"))
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38 38)
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(define_function_unit "imuldiv" 1 0
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@ -308,12 +308,12 @@
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "idiv")
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(and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r4320")))
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(and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300")))
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37 37)
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "idiv")
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(and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300,r4320")))
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(and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
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69 69)
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(define_function_unit "imuldiv" 1 0
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@ -334,7 +334,7 @@
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;; instructions to be processed in the "imuldiv" unit.
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(define_function_unit "adder" 1 1
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(and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r4320,r5000"))
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(and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))
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3 0)
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(define_function_unit "adder" 1 1
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@ -346,7 +346,7 @@
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1 0)
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(define_function_unit "adder" 1 1
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(and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r4320"))
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(and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300"))
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4 0)
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(define_function_unit "adder" 1 1
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@ -359,7 +359,7 @@
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(define_function_unit "adder" 1 1
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(and (eq_attr "type" "fabs,fneg")
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(eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r4320,r5000"))
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(eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
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2 0)
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(define_function_unit "adder" 1 1
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@ -369,7 +369,7 @@
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(define_function_unit "mult" 1 1
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(and (eq_attr "type" "fmul")
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(and (eq_attr "mode" "SF")
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(eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r4320,r5000")))
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(eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
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7 0)
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(define_function_unit "mult" 1 1
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@ -389,7 +389,7 @@
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(define_function_unit "mult" 1 1
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(and (eq_attr "type" "fmul")
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r4320,r5000")))
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")))
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8 0)
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(define_function_unit "mult" 1 1
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@ -405,7 +405,7 @@
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(define_function_unit "divide" 1 1
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(and (eq_attr "type" "fdiv")
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(and (eq_attr "mode" "SF")
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(eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r4320,r5000")))
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(eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
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23 0)
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(define_function_unit "divide" 1 1
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@ -431,7 +431,7 @@
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(define_function_unit "divide" 1 1
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(and (eq_attr "type" "fdiv")
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(and (eq_attr "mode" "DF")
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(eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r4320")))
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(eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300")))
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36 0)
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(define_function_unit "divide" 1 1
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@ -452,7 +452,7 @@
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;;; ??? Is this number right?
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(define_function_unit "divide" 1 1
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(and (eq_attr "type" "fsqrt,frsqrt")
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(and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r4320,r5000")))
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(and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
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54 0)
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(define_function_unit "divide" 1 1
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@ -468,7 +468,7 @@
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;;; ??? Is this number right?
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(define_function_unit "divide" 1 1
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(and (eq_attr "type" "fsqrt,frsqrt")
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r4320,r5000")))
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
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112 0)
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(define_function_unit "divide" 1 1
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@ -485,27 +485,27 @@
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;; functional unit:
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300,r4320"))
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(and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300"))
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3 3)
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300,r4320"))
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(and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300"))
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1 1)
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300,r4320")))
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(and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
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5 5)
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300,r4320")))
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(and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
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8 8)
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(define_function_unit "imuldiv" 1 0
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(and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
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(and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300,r4320")))
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(and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
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29 29)
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(define_function_unit "imuldiv" 1 0
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(and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300,r4320")))
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(and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
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58 58)
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;; The following functional units do not use the cpu type, and use
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@ -1694,8 +1694,7 @@
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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"
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{
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if (!TARGET_MIPS4300
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&& !TARGET_MIPS4320)
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if (!TARGET_MIPS4300)
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emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
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else
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emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
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@ -1706,8 +1705,7 @@
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[(set (match_operand:DF 0 "register_operand" "=f")
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(mult:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
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&& !TARGET_MIPS4300 &&!TARGET_MIPS4320"
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_MIPS4300"
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"mul.d\\t%0,%1,%2"
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[(set_attr "type" "fmul")
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(set_attr "mode" "DF")])
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@ -1716,8 +1714,7 @@
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[(set (match_operand:DF 0 "register_operand" "=f")
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(mult:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
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&& (TARGET_MIPS4300 || TARGET_MIPS4320)"
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_MIPS4300"
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"*
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{
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output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
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@ -1736,7 +1733,7 @@
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"TARGET_HARD_FLOAT"
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"
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{
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if (!TARGET_MIPS4300 && !TARGET_MIPS4320)
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if (!TARGET_MIPS4300)
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emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
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else
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emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
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@ -1747,8 +1744,7 @@
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[(set (match_operand:SF 0 "register_operand" "=f")
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(mult:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT
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&& !TARGET_MIPS4300 && !TARGET_MIPS4320"
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"TARGET_HARD_FLOAT && !TARGET_MIPS4300"
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"mul.s\\t%0,%1,%2"
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[(set_attr "type" "fmul")
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(set_attr "mode" "SF")])
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@ -1757,8 +1753,7 @@
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[(set (match_operand:SF 0 "register_operand" "=f")
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(mult:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT
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&& (TARGET_MIPS4300 || TARGET_MIPS4320)"
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"TARGET_HARD_FLOAT && TARGET_MIPS4300"
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"*
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{
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output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
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@ -1809,7 +1804,6 @@
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if (TARGET_MAD
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|| TARGET_MIPS5400
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|| TARGET_MIPS5500
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|| TARGET_MIPS4320
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|| ISA_MIPS32
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|| ISA_MIPS64)
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return \"mul\\t%0,%1,%2\";
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@ -1874,7 +1868,6 @@
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(clobber (match_scratch:SI 6 "=a,a,a"))
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(clobber (match_scratch:SI 7 "=X,X,d"))]
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"(TARGET_MIPS3900
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|| TARGET_MIPS4320
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|| TARGET_MIPS5400
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|| TARGET_MIPS5500
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|| ISA_HAS_MADD_MSUB)
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@ -1899,9 +1892,6 @@
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return macc[which_alternative];
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}
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if (TARGET_MIPS4320)
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return macc[which_alternative];
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return madd[which_alternative];
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}"
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[(set_attr "type" "imadd,imadd,multi")
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