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sync.md (sync_compare_and_swap<mode>, [...]): Rewrite calls to mips_output_sync_loop.
2009-08-05 David Daney <ddaney@caviumnetworks.com> * gcc/config/mips/sync.md (sync_compare_and_swap<mode>, compare_and_swap_12, sync_add<mode>, sync_<optab>_12, sync_old_<optab>_12, sync_new_<optab>_12, sync_nand_12, sync_old_nand_12, sync_new_nand_12, sync_sub<mode>, sync_old_add<mode>, sync_old_sub<mode>, sync_new_add<mode>, sync_new_sub<mode>, sync_<optab><mode>, sync_old_<optab><mode>, sync_new_<optab><mode>, sync_nand<mode>, sync_old_nand<mode>, sync_new_nand<mode>, sync_lock_test_and_set<mode>, test_and_set_12): Rewrite calls to mips_output_sync_loop. * gcc/config/mips/mips-protos.h (mips_output_sync_loop): Make the prototype declaration match the definition. * gcc/config/mips/mips.c (mips_output_sync_loop): Emit sync instructions explicitly. Add barrier_before and operands parameters. * gcc/config/mips/mips.h (MIPS_COMPARE_AND_SWAP, MIPS_COMPARE_AND_SWAP_12, MIPS_SYNC_OP, MIPS_SYNC_OP_12, MIPS_SYNC_OLD_OP_12, MIPS_SYNC_NEW_OP_12, MIPS_SYNC_OLD_OP, MIPS_SYNC_NEW_OP, MIPS_SYNC_NAND, MIPS_SYNC_OLD_NAND, MIPS_SYNC_NEW_NAND, MIPS_SYNC_EXCHANGE, MIPS_SYNC_EXCHANGE_12): Remove sync instructions. From-SVN: r150512
This commit is contained in:
David Daney
David Daney
parent
60376e9d19
commit
40a4a37bd7
@ -1,3 +1,26 @@
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2009-08-05 David Daney <ddaney@caviumnetworks.com>
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* gcc/config/mips/sync.md (sync_compare_and_swap<mode>,
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compare_and_swap_12, sync_add<mode>, sync_<optab>_12,
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sync_old_<optab>_12, sync_new_<optab>_12, sync_nand_12,
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sync_old_nand_12, sync_new_nand_12, sync_sub<mode>,
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sync_old_add<mode>, sync_old_sub<mode>, sync_new_add<mode>,
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sync_new_sub<mode>, sync_<optab><mode>, sync_old_<optab><mode>,
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sync_new_<optab><mode>, sync_nand<mode>, sync_old_nand<mode>,
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sync_new_nand<mode>, sync_lock_test_and_set<mode>,
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test_and_set_12): Rewrite calls to mips_output_sync_loop.
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* gcc/config/mips/mips-protos.h (mips_output_sync_loop): Make
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the prototype declaration match the definition.
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* gcc/config/mips/mips.c (mips_output_sync_loop): Emit sync
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instructions explicitly. Add barrier_before and operands
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parameters.
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* gcc/config/mips/mips.h (MIPS_COMPARE_AND_SWAP,
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MIPS_COMPARE_AND_SWAP_12, MIPS_SYNC_OP, MIPS_SYNC_OP_12,
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MIPS_SYNC_OLD_OP_12, MIPS_SYNC_NEW_OP_12, MIPS_SYNC_OLD_OP,
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MIPS_SYNC_NEW_OP, MIPS_SYNC_NAND, MIPS_SYNC_OLD_NAND,
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MIPS_SYNC_NEW_NAND, MIPS_SYNC_EXCHANGE,
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MIPS_SYNC_EXCHANGE_12): Remove sync instructions.
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2009-08-05 Andrew Pinski <pinskia@gmail.com>
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* tree-ssa-alias.c: Fix intervals to use [) syntax.
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@ -298,7 +298,7 @@ extern const char *mips_output_load_label (void);
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extern const char *mips_output_conditional_branch (rtx, rtx *, const char *,
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const char *);
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extern const char *mips_output_order_conditional_branch (rtx, rtx *, bool);
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extern const char *mips_output_sync_loop (const char *);
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extern const char *mips_output_sync_loop (bool, const char *, rtx *);
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extern const char *mips_output_division (const char *, rtx *);
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extern unsigned int mips_hard_regno_nregs (int, enum machine_mode);
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extern bool mips_linked_madd_p (rtx, rtx);
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@ -10750,15 +10750,23 @@ mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
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return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
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}
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/* Return the assembly code for __sync_*() loop LOOP. The loop should support
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both normal and likely branches, using %? and %~ where appropriate. */
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/* Return or emit the assembly code for __sync_*() loop LOOP. The
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loop should support both normal and likely branches, using %? and
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%~ where appropriate. If BARRIER_BEFORE is true a sync sequence is
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emitted before the loop. A sync is always emitted after the loop.
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OPERANDS are the insn operands. */
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const char *
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mips_output_sync_loop (const char *loop)
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mips_output_sync_loop (bool barrier_before,
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const char *loop, rtx *operands)
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{
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if (barrier_before)
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output_asm_insn ("sync", NULL);
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/* Use branch-likely instructions to work around the LL/SC R10000 errata. */
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mips_branch_likely = TARGET_FIX_R10000;
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return loop;
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output_asm_insn (loop, operands);
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return "sync";
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}
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/* Return the assembly code for DIV or DDIV instruction DIVISION, which has
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@ -3144,14 +3144,12 @@ while (0)
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and OP is the instruction that should be used to load %3 into a
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register. */
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#define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
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"%(%<%[%|sync\n" \
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"1:\tll" SUFFIX "\t%0,%1\n" \
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"%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
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"\tbne\t%0,%z2,2f\n" \
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"\t" OP "\t%@,%3\n" \
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"\tsc" SUFFIX "\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)\n" \
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"\tnop%-%]%>%)\n" \
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"2:\n"
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/* Return an asm string that atomically:
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@ -3167,16 +3165,14 @@ while (0)
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OPS are the instructions needed to OR %5 with %@. */
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#define MIPS_COMPARE_AND_SWAP_12(OPS) \
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"%(%<%[%|sync\n" \
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"1:\tll\t%0,%1\n" \
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"%(%<%[%|1:\tll\t%0,%1\n" \
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"\tand\t%@,%0,%2\n" \
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"\tbne\t%@,%z4,2f\n" \
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"\tand\t%@,%0,%3\n" \
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OPS \
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"\tsc\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)\n" \
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"\tnop%-%]%>%)\n" \
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"2:\n"
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#define MIPS_COMPARE_AND_SWAP_12_ZERO_OP ""
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@ -3190,13 +3186,11 @@ while (0)
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SUFFIX is the suffix that should be added to "ll" and "sc"
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instructions. */
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#define MIPS_SYNC_OP(SUFFIX, INSN) \
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"%(%<%[%|sync\n" \
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"1:\tll" SUFFIX "\t%@,%0\n" \
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"%(%<%[%|1:\tll" SUFFIX "\t%@,%0\n" \
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"\t" INSN "\t%@,%@,%1\n" \
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"\tsc" SUFFIX "\t%@,%0\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)"
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"\tnop%-%]%>%)"
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/* Return an asm string that atomically:
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@ -3213,16 +3207,14 @@ while (0)
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INSN is already correctly masked -- it instead performs a bitwise
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not. */
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#define MIPS_SYNC_OP_12(INSN, AND_OP) \
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"%(%<%[%|sync\n" \
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"1:\tll\t%4,%0\n" \
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"%(%<%[%|1:\tll\t%4,%0\n" \
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"\tand\t%@,%4,%2\n" \
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"\t" INSN "\t%4,%4,%z3\n" \
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AND_OP \
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"\tor\t%@,%@,%4\n" \
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"\tsc\t%@,%0\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)"
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"\tnop%-%]%>%)"
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#define MIPS_SYNC_OP_12_AND "\tand\t%4,%4,%1\n"
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#define MIPS_SYNC_OP_12_XOR "\txor\t%4,%4,%1\n"
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@ -3244,16 +3236,14 @@ while (0)
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INSN is already correctly masked -- it instead performs a bitwise
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not. */
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#define MIPS_SYNC_OLD_OP_12(INSN, AND_OP) \
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"%(%<%[%|sync\n" \
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"1:\tll\t%0,%1\n" \
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"%(%<%[%|1:\tll\t%0,%1\n" \
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"\tand\t%@,%0,%3\n" \
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"\t" INSN "\t%5,%0,%z4\n" \
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AND_OP \
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"\tor\t%@,%@,%5\n" \
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"\tsc\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)"
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"\tnop%-%]%>%)"
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#define MIPS_SYNC_OLD_OP_12_AND "\tand\t%5,%5,%2\n"
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#define MIPS_SYNC_OLD_OP_12_XOR "\txor\t%5,%5,%2\n"
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@ -3273,16 +3263,14 @@ while (0)
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INSN is already correctly masked -- it instead performs a bitwise
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not. */
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#define MIPS_SYNC_NEW_OP_12(INSN, AND_OP) \
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"%(%<%[%|sync\n" \
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"1:\tll\t%0,%1\n" \
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"%(%<%[%|1:\tll\t%0,%1\n" \
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"\tand\t%@,%0,%3\n" \
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"\t" INSN "\t%0,%0,%z4\n" \
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AND_OP \
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"\tor\t%@,%@,%0\n" \
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"\tsc\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)"
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"\tnop%-%]%>%)"
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#define MIPS_SYNC_NEW_OP_12_AND "\tand\t%0,%0,%2\n"
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#define MIPS_SYNC_NEW_OP_12_XOR "\txor\t%0,%0,%2\n"
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@ -3296,13 +3284,11 @@ while (0)
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SUFFIX is the suffix that should be added to "ll" and "sc"
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instructions. */
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#define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
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"%(%<%[%|sync\n" \
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"1:\tll" SUFFIX "\t%0,%1\n" \
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"%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
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"\t" INSN "\t%@,%0,%2\n" \
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"\tsc" SUFFIX "\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)"
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"\tnop%-%]%>%)"
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/* Return an asm string that atomically:
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@ -3313,13 +3299,11 @@ while (0)
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SUFFIX is the suffix that should be added to "ll" and "sc"
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instructions. */
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#define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
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"%(%<%[%|sync\n" \
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"1:\tll" SUFFIX "\t%0,%1\n" \
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"%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
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"\t" INSN "\t%@,%0,%2\n" \
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"\tsc" SUFFIX "\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b%~\n" \
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"\t" INSN "\t%0,%0,%2\n" \
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"\tsync%-%]%>%)"
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"\t" INSN "\t%0,%0,%2%-%]%>%)"
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/* Return an asm string that atomically:
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@ -3329,14 +3313,12 @@ while (0)
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instructions. INSN is the and instruction needed to and a register
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with %2. */
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#define MIPS_SYNC_NAND(SUFFIX, INSN) \
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"%(%<%[%|sync\n" \
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"1:\tll" SUFFIX "\t%@,%0\n" \
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"%(%<%[%|1:\tll" SUFFIX "\t%@,%0\n" \
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"\t" INSN "\t%@,%@,%1\n" \
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"\tnor\t%@,%@,%.\n" \
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"\tsc" SUFFIX "\t%@,%0\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)"
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"\tnop%-%]%>%)"
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/* Return an asm string that atomically:
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@ -3348,14 +3330,12 @@ while (0)
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instructions. INSN is the and instruction needed to and a register
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with %2. */
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#define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
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"%(%<%[%|sync\n" \
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"1:\tll" SUFFIX "\t%0,%1\n" \
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"%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
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"\t" INSN "\t%@,%0,%2\n" \
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"\tnor\t%@,%@,%.\n" \
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"\tsc" SUFFIX "\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)"
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"\tnop%-%]%>%)"
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/* Return an asm string that atomically:
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@ -3367,14 +3347,12 @@ while (0)
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instructions. INSN is the and instruction needed to and a register
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with %2. */
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#define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
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"%(%<%[%|sync\n" \
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"1:\tll" SUFFIX "\t%0,%1\n" \
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"%(%<%[%|1:\tll" SUFFIX "\t%0,%1\n" \
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"\t" INSN "\t%0,%0,%2\n" \
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"\tnor\t%@,%0,%.\n" \
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"\tsc" SUFFIX "\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b%~\n" \
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"\tnor\t%0,%0,%.\n" \
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"\tsync%-%]%>%)"
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"\tnor\t%0,%0,%.%-%]%>%)"
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/* Return an asm string that atomically:
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@ -3391,8 +3369,7 @@ while (0)
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"\t" OP "\t%@,%2\n" \
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"\tsc" SUFFIX "\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)"
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"\tnop%-%]%>%)"
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/* Return an asm string that atomically:
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@ -3415,8 +3392,7 @@ while (0)
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OPS \
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"\tsc\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)"
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"\tnop%-%]%>%)"
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#define MIPS_SYNC_EXCHANGE_12_ZERO_OP ""
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#define MIPS_SYNC_EXCHANGE_12_NONZERO_OP "\tor\t%@,%@,%4\n"
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@ -51,10 +51,12 @@
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UNSPEC_COMPARE_AND_SWAP))]
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"GENERATE_LL_SC"
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{
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const char *loop;
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if (which_alternative == 0)
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return mips_output_sync_loop (MIPS_COMPARE_AND_SWAP ("<d>", "li"));
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loop = MIPS_COMPARE_AND_SWAP ("<d>", "li");
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else
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return mips_output_sync_loop (MIPS_COMPARE_AND_SWAP ("<d>", "move"));
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loop = MIPS_COMPARE_AND_SWAP ("<d>", "move");
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return mips_output_sync_loop (true, loop, operands);
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}
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[(set_attr "length" "32")])
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@ -84,12 +86,12 @@
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UNSPEC_COMPARE_AND_SWAP_12))]
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"GENERATE_LL_SC"
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{
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const char *loop;
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if (which_alternative == 0)
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return (mips_output_sync_loop
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(MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_NONZERO_OP)));
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loop = MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_NONZERO_OP);
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else
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return (mips_output_sync_loop
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(MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_ZERO_OP)));
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loop = MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_ZERO_OP);
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return mips_output_sync_loop (true, loop, operands);
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}
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[(set_attr "length" "40,36")])
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@ -101,10 +103,12 @@
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UNSPEC_SYNC_OLD_OP))]
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"GENERATE_LL_SC"
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{
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const char *loop;
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if (which_alternative == 0)
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return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<d>addiu"));
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loop = MIPS_SYNC_OP ("<d>", "<d>addiu");
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else
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return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<d>addu"));
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loop = MIPS_SYNC_OP ("<d>", "<d>addu");
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return mips_output_sync_loop (true, loop, operands);
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}
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[(set_attr "length" "28")])
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@ -135,8 +139,8 @@
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(clobber (match_scratch:SI 4 "=&d"))]
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"GENERATE_LL_SC"
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{
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return (mips_output_sync_loop
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(MIPS_SYNC_OP_12 ("<insn>", MIPS_SYNC_OP_12_AND)));
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const char *loop = MIPS_SYNC_OP_12 ("<insn>", MIPS_SYNC_OP_12_AND);
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return mips_output_sync_loop (true, loop, operands);
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}
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[(set_attr "length" "40")])
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@ -172,8 +176,8 @@
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(clobber (match_scratch:SI 5 "=&d"))]
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"GENERATE_LL_SC"
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{
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return (mips_output_sync_loop
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(MIPS_SYNC_OLD_OP_12 ("<insn>", MIPS_SYNC_OLD_OP_12_AND)));
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const char *loop = MIPS_SYNC_OLD_OP_12 ("<insn>", MIPS_SYNC_OLD_OP_12_AND);
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "40")])
|
||||
|
||||
@ -214,8 +218,8 @@
|
||||
(match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
return (mips_output_sync_loop
|
||||
(MIPS_SYNC_NEW_OP_12 ("<insn>", MIPS_SYNC_NEW_OP_12_AND)));
|
||||
const char *loop = MIPS_SYNC_NEW_OP_12 ("<insn>", MIPS_SYNC_NEW_OP_12_AND);
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "40")])
|
||||
|
||||
@ -246,8 +250,8 @@
|
||||
(clobber (match_scratch:SI 4 "=&d"))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
return (mips_output_sync_loop
|
||||
(MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_XOR)));
|
||||
const char *loop = MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_XOR);
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "40")])
|
||||
|
||||
@ -281,8 +285,8 @@
|
||||
(clobber (match_scratch:SI 5 "=&d"))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
return (mips_output_sync_loop
|
||||
(MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_XOR)));
|
||||
const char *loop = MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_XOR);
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "40")])
|
||||
|
||||
@ -321,8 +325,8 @@
|
||||
(match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
return (mips_output_sync_loop
|
||||
(MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_XOR)));
|
||||
const char *loop = MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_XOR);
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "40")])
|
||||
|
||||
@ -334,7 +338,8 @@
|
||||
UNSPEC_SYNC_OLD_OP))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<d>subu"));
|
||||
const char *loop = MIPS_SYNC_OP ("<d>", "<d>subu");
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "28")])
|
||||
|
||||
@ -348,10 +353,12 @@
|
||||
UNSPEC_SYNC_OLD_OP))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
const char *loop;
|
||||
if (which_alternative == 0)
|
||||
return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<d>addiu"));
|
||||
loop = MIPS_SYNC_OLD_OP ("<d>", "<d>addiu");
|
||||
else
|
||||
return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<d>addu"));
|
||||
loop = MIPS_SYNC_OLD_OP ("<d>", "<d>addu");
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "28")])
|
||||
|
||||
@ -365,7 +372,8 @@
|
||||
UNSPEC_SYNC_OLD_OP))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<d>subu"));
|
||||
const char *loop = MIPS_SYNC_OLD_OP ("<d>", "<d>subu");
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "28")])
|
||||
|
||||
@ -379,10 +387,12 @@
|
||||
UNSPEC_SYNC_NEW_OP))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
const char *loop;
|
||||
if (which_alternative == 0)
|
||||
return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<d>addiu"));
|
||||
loop = MIPS_SYNC_NEW_OP ("<d>", "<d>addiu");
|
||||
else
|
||||
return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<d>addu"));
|
||||
loop = MIPS_SYNC_NEW_OP ("<d>", "<d>addu");
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "28")])
|
||||
|
||||
@ -396,7 +406,8 @@
|
||||
UNSPEC_SYNC_NEW_OP))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<d>subu"));
|
||||
const char *loop = MIPS_SYNC_NEW_OP ("<d>", "<d>subu");
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "28")])
|
||||
|
||||
@ -408,10 +419,12 @@
|
||||
UNSPEC_SYNC_OLD_OP))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
const char *loop;
|
||||
if (which_alternative == 0)
|
||||
return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<immediate_insn>"));
|
||||
loop = MIPS_SYNC_OP ("<d>", "<immediate_insn>");
|
||||
else
|
||||
return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<insn>"));
|
||||
loop = MIPS_SYNC_OP ("<d>", "<insn>");
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "28")])
|
||||
|
||||
@ -425,11 +438,12 @@
|
||||
UNSPEC_SYNC_OLD_OP))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
const char *loop;
|
||||
if (which_alternative == 0)
|
||||
return (mips_output_sync_loop
|
||||
(MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>")));
|
||||
loop = MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>");
|
||||
else
|
||||
return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<insn>"));
|
||||
loop = MIPS_SYNC_OLD_OP ("<d>", "<insn>");
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "28")])
|
||||
|
||||
@ -443,11 +457,12 @@
|
||||
UNSPEC_SYNC_NEW_OP))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
const char *loop;
|
||||
if (which_alternative == 0)
|
||||
return (mips_output_sync_loop
|
||||
(MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>")));
|
||||
loop = MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>");
|
||||
else
|
||||
return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<insn>"));
|
||||
loop = MIPS_SYNC_NEW_OP ("<d>", "<insn>");
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "28")])
|
||||
|
||||
@ -457,10 +472,12 @@
|
||||
UNSPEC_SYNC_OLD_OP))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
const char *loop;
|
||||
if (which_alternative == 0)
|
||||
return mips_output_sync_loop (MIPS_SYNC_NAND ("<d>", "andi"));
|
||||
loop = MIPS_SYNC_NAND ("<d>", "andi");
|
||||
else
|
||||
return mips_output_sync_loop (MIPS_SYNC_NAND ("<d>", "and"));
|
||||
loop = MIPS_SYNC_NAND ("<d>", "and");
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "32")])
|
||||
|
||||
@ -472,10 +489,12 @@
|
||||
UNSPEC_SYNC_OLD_OP))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
const char *loop;
|
||||
if (which_alternative == 0)
|
||||
return mips_output_sync_loop (MIPS_SYNC_OLD_NAND ("<d>", "andi"));
|
||||
loop = MIPS_SYNC_OLD_NAND ("<d>", "andi");
|
||||
else
|
||||
return mips_output_sync_loop (MIPS_SYNC_OLD_NAND ("<d>", "and"));
|
||||
loop = MIPS_SYNC_OLD_NAND ("<d>", "and");
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "32")])
|
||||
|
||||
@ -487,10 +506,12 @@
|
||||
UNSPEC_SYNC_NEW_OP))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
const char *loop;
|
||||
if (which_alternative == 0)
|
||||
return mips_output_sync_loop (MIPS_SYNC_NEW_NAND ("<d>", "andi"));
|
||||
loop = MIPS_SYNC_NEW_NAND ("<d>", "andi");
|
||||
else
|
||||
return mips_output_sync_loop (MIPS_SYNC_NEW_NAND ("<d>", "and"));
|
||||
loop = MIPS_SYNC_NEW_NAND ("<d>", "and");
|
||||
return mips_output_sync_loop (true, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "32")])
|
||||
|
||||
@ -502,10 +523,12 @@
|
||||
UNSPEC_SYNC_EXCHANGE))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
const char *loop;
|
||||
if (which_alternative == 0)
|
||||
return mips_output_sync_loop (MIPS_SYNC_EXCHANGE ("<d>", "li"));
|
||||
loop = MIPS_SYNC_EXCHANGE ("<d>", "li");
|
||||
else
|
||||
return mips_output_sync_loop (MIPS_SYNC_EXCHANGE ("<d>", "move"));
|
||||
loop = MIPS_SYNC_EXCHANGE ("<d>", "move");
|
||||
return mips_output_sync_loop (false, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "24")])
|
||||
|
||||
@ -532,11 +555,11 @@
|
||||
UNSPEC_SYNC_EXCHANGE_12))]
|
||||
"GENERATE_LL_SC"
|
||||
{
|
||||
const char *loop;
|
||||
if (which_alternative == 0)
|
||||
return (mips_output_sync_loop
|
||||
(MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_NONZERO_OP)));
|
||||
loop = MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_NONZERO_OP);
|
||||
else
|
||||
return (mips_output_sync_loop
|
||||
(MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_ZERO_OP)));
|
||||
loop = MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_ZERO_OP);
|
||||
return mips_output_sync_loop (false, loop, operands);
|
||||
}
|
||||
[(set_attr "length" "28,24")])
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user