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arm.c (arm_emit_coreregs_64bit_shift): Fix comment.
2012-11-13 Andrew Stubbs <ams@codesourcery.com>
Ulrich Weigand <ulrich.weigand@linaro.org>
* config/arm/arm.c (arm_emit_coreregs_64bit_shift): Fix comment.
* config/arm/arm.md (opt, opt_enabled): New attributes.
(enabled): Use opt_enabled.
(ashldi3, ashrdi3, lshrdi3): Add TARGET_NEON case.
(ashldi3): Allow general operands for TARGET_NEON case.
* config/arm/iterators.md (rshifts): New code iterator.
(shift, shifttype): New code attributes.
* config/arm/neon.md (UNSPEC_LOAD_COUNT): New unspec type.
(neon_load_count, ashldi3_neon_noclobber, ashldi3_neon,
signed_shift_di3_neon, unsigned_shift_di3_neon,
ashrdi3_neon_imm_noclobber, lshrdi3_neon_imm_noclobber,
<shift>di3_neon): New patterns.
Co-Authored-By: Ulrich Weigand <ulrich.weigand@linaro.org>
From-SVN: r193476
This commit is contained in:
Andrew Stubbs
Ulrich Weigand
parent
2b12109c4a
commit
3f2dc80614
gcc
@ -1,3 +1,19 @@
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2012-11-13 Andrew Stubbs <ams@codesourcery.com>
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Ulrich Weigand <ulrich.weigand@linaro.org>
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* config/arm/arm.c (arm_emit_coreregs_64bit_shift): Fix comment.
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* config/arm/arm.md (opt, opt_enabled): New attributes.
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(enabled): Use opt_enabled.
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(ashldi3, ashrdi3, lshrdi3): Add TARGET_NEON case.
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(ashldi3): Allow general operands for TARGET_NEON case.
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* config/arm/iterators.md (rshifts): New code iterator.
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(shift, shifttype): New code attributes.
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* config/arm/neon.md (UNSPEC_LOAD_COUNT): New unspec type.
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(neon_load_count, ashldi3_neon_noclobber, ashldi3_neon,
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signed_shift_di3_neon, unsigned_shift_di3_neon,
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ashrdi3_neon_imm_noclobber, lshrdi3_neon_imm_noclobber,
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<shift>di3_neon): New patterns.
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2012-11-13 Jakub Jelinek <jakub@redhat.com>
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* Makefile.in (asan.o): Depend on $(TM_P_H).
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@ -26635,8 +26635,7 @@ arm_autoinc_modes_ok_p (enum machine_mode mode, enum arm_auto_incmodes code)
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Input requirements:
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- It is safe for the input and output to be the same register, but
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early-clobber rules apply for the shift amount and scratch registers.
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- Shift by register requires both scratch registers. Shift by a constant
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less than 32 in Thumb2 mode requires SCRATCH1 only. In all other cases
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- Shift by register requires both scratch registers. In all other cases
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the scratch registers may be NULL.
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- Ashiftrt by a register also clobbers the CC register. */
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void
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@ -249,6 +249,22 @@
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(const_string "no")))
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(define_attr "opt" "any,speed,size"
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(const_string "any"))
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(define_attr "opt_enabled" "no,yes"
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(cond [(eq_attr "opt" "any")
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(const_string "yes")
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(and (eq_attr "opt" "speed")
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(match_test "optimize_function_for_speed_p (cfun)"))
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(const_string "yes")
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(and (eq_attr "opt" "size")
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(match_test "optimize_function_for_size_p (cfun)"))
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(const_string "yes")]
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(const_string "no")))
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; Allows an insn to disable certain alternatives for reasons other than
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; arch support.
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(define_attr "insn_enabled" "no,yes"
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@ -256,11 +272,15 @@
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; Enable all alternatives that are both arch_enabled and insn_enabled.
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(define_attr "enabled" "no,yes"
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(if_then_else (eq_attr "insn_enabled" "yes")
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(if_then_else (eq_attr "arch_enabled" "yes")
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(const_string "yes")
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(const_string "no"))
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(const_string "no")))
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(cond [(eq_attr "insn_enabled" "no")
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(const_string "no")
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(eq_attr "arch_enabled" "no")
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(const_string "no")
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(eq_attr "opt_enabled" "no")
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(const_string "no")]
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(const_string "yes")))
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; POOL_RANGE is how far away from a constant pool entry that this insn
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; can be placed. If the distance is zero, then this insn will never
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@ -3489,9 +3509,23 @@
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(define_expand "ashldi3"
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[(set (match_operand:DI 0 "s_register_operand" "")
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(ashift:DI (match_operand:DI 1 "s_register_operand" "")
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(match_operand:SI 2 "reg_or_int_operand" "")))]
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(match_operand:SI 2 "general_operand" "")))]
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"TARGET_32BIT"
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"
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if (TARGET_NEON)
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{
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/* Delay the decision whether to use NEON or core-regs until
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register allocation. */
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emit_insn (gen_ashldi3_neon (operands[0], operands[1], operands[2]));
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DONE;
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}
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else
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{
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/* Only the NEON case can handle in-memory shift counts. */
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if (!reg_or_int_operand (operands[2], SImode))
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operands[2] = force_reg (SImode, operands[2]);
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}
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if (!CONST_INT_P (operands[2]) && TARGET_REALLY_IWMMXT)
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; /* No special preparation statements; expand pattern as above. */
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else
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@ -3566,6 +3600,14 @@
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(match_operand:SI 2 "reg_or_int_operand" "")))]
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"TARGET_32BIT"
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"
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if (TARGET_NEON)
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{
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/* Delay the decision whether to use NEON or core-regs until
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register allocation. */
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emit_insn (gen_ashrdi3_neon (operands[0], operands[1], operands[2]));
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DONE;
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}
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if (!CONST_INT_P (operands[2]) && TARGET_REALLY_IWMMXT)
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; /* No special preparation statements; expand pattern as above. */
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else
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@ -3638,6 +3680,14 @@
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(match_operand:SI 2 "reg_or_int_operand" "")))]
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"TARGET_32BIT"
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"
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if (TARGET_NEON)
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{
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/* Delay the decision whether to use NEON or core-regs until
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register allocation. */
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emit_insn (gen_lshrdi3_neon (operands[0], operands[1], operands[2]));
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DONE;
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}
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if (!CONST_INT_P (operands[2]) && TARGET_REALLY_IWMMXT)
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; /* No special preparation statements; expand pattern as above. */
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else
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@ -188,6 +188,9 @@
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;; A list of widening operators
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(define_code_iterator SE [sign_extend zero_extend])
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;; Right shifts
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(define_code_iterator rshifts [ashiftrt lshiftrt])
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;;----------------------------------------------------------------------------
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;; Mode attributes
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;;----------------------------------------------------------------------------
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@ -449,3 +452,8 @@
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;; Assembler mnemonics for signedness of widening operations.
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(define_code_attr US [(sign_extend "s") (zero_extend "u")])
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;; Right shifts
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(define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")])
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(define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")])
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@ -23,6 +23,7 @@
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(define_c_enum "unspec" [
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UNSPEC_ASHIFT_SIGNED
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UNSPEC_ASHIFT_UNSIGNED
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UNSPEC_LOAD_COUNT
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UNSPEC_VABD
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UNSPEC_VABDL
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UNSPEC_VADD
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@ -1200,6 +1201,189 @@
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DONE;
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})
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;; 64-bit shifts
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;; This pattern loads a 32-bit shift count into a 64-bit NEON register,
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;; leaving the upper half uninitalized. This is OK since the shift
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;; instruction only looks at the low 8 bits anyway. To avoid confusing
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;; data flow analysis however, we pretend the full register is set
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;; using an unspec.
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(define_insn "neon_load_count"
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[(set (match_operand:DI 0 "s_register_operand" "=w,w")
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(unspec:DI [(match_operand:SI 1 "nonimmediate_operand" "Um,r")]
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UNSPEC_LOAD_COUNT))]
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"TARGET_NEON"
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"@
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vld1.32\t{%P0[0]}, %A1
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vmov.32\t%P0[0], %1"
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[(set_attr "neon_type" "neon_vld1_vld2_lane,neon_mcr")]
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)
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(define_insn "ashldi3_neon_noclobber"
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[(set (match_operand:DI 0 "s_register_operand" "=w,w")
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(ashift:DI (match_operand:DI 1 "s_register_operand" " w,w")
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(match_operand:DI 2 "reg_or_int_operand" " i,w")))]
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"TARGET_NEON && reload_completed
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&& (!CONST_INT_P (operands[2])
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|| (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 64))"
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"@
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vshl.u64\t%P0, %P1, %2
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vshl.u64\t%P0, %P1, %P2"
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[(set_attr "neon_type" "neon_vshl_ddd,neon_vshl_ddd")]
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)
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(define_insn_and_split "ashldi3_neon"
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[(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r, ?w,w")
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(ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r, 0w,w")
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(match_operand:SI 2 "general_operand" "rUm, i, r, i,rUm,i")))
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(clobber (match_scratch:SI 3 "= X, X,?&r, X, X,X"))
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(clobber (match_scratch:SI 4 "= X, X,?&r, X, X,X"))
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(clobber (match_scratch:DI 5 "=&w, X, X, X, &w,X"))
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(clobber (reg:CC_C CC_REGNUM))]
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"TARGET_NEON"
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"#"
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"TARGET_NEON && reload_completed"
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[(const_int 0)]
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"
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{
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if (IS_VFP_REGNUM (REGNO (operands[0])))
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{
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if (CONST_INT_P (operands[2]))
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{
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if (INTVAL (operands[2]) < 1)
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{
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emit_insn (gen_movdi (operands[0], operands[1]));
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DONE;
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}
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else if (INTVAL (operands[2]) > 63)
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operands[2] = gen_rtx_CONST_INT (VOIDmode, 63);
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}
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else
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{
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emit_insn (gen_neon_load_count (operands[5], operands[2]));
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operands[2] = operands[5];
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}
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/* Ditch the unnecessary clobbers. */
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emit_insn (gen_ashldi3_neon_noclobber (operands[0], operands[1],
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operands[2]));
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}
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else
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{
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if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
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/* This clobbers CC. */
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emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1]));
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else
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arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1],
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operands[2], operands[3], operands[4]);
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}
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DONE;
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}"
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[(set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")
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(set_attr "opt" "*,*,speed,speed,*,*")]
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)
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; The shift amount needs to be negated for right-shifts
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(define_insn "signed_shift_di3_neon"
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[(set (match_operand:DI 0 "s_register_operand" "=w")
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(unspec:DI [(match_operand:DI 1 "s_register_operand" " w")
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(match_operand:DI 2 "s_register_operand" " w")]
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UNSPEC_ASHIFT_SIGNED))]
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"TARGET_NEON && reload_completed"
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"vshl.s64\t%P0, %P1, %P2"
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[(set_attr "neon_type" "neon_vshl_ddd")]
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)
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; The shift amount needs to be negated for right-shifts
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(define_insn "unsigned_shift_di3_neon"
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[(set (match_operand:DI 0 "s_register_operand" "=w")
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(unspec:DI [(match_operand:DI 1 "s_register_operand" " w")
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(match_operand:DI 2 "s_register_operand" " w")]
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UNSPEC_ASHIFT_UNSIGNED))]
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"TARGET_NEON && reload_completed"
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"vshl.u64\t%P0, %P1, %P2"
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[(set_attr "neon_type" "neon_vshl_ddd")]
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)
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(define_insn "ashrdi3_neon_imm_noclobber"
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[(set (match_operand:DI 0 "s_register_operand" "=w")
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(ashiftrt:DI (match_operand:DI 1 "s_register_operand" " w")
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(match_operand:DI 2 "const_int_operand" " i")))]
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"TARGET_NEON && reload_completed
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&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 64"
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"vshr.s64\t%P0, %P1, %2"
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[(set_attr "neon_type" "neon_vshl_ddd")]
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)
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(define_insn "lshrdi3_neon_imm_noclobber"
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[(set (match_operand:DI 0 "s_register_operand" "=w")
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(lshiftrt:DI (match_operand:DI 1 "s_register_operand" " w")
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(match_operand:DI 2 "const_int_operand" " i")))]
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"TARGET_NEON && reload_completed
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&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 64"
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"vshr.u64\t%P0, %P1, %2"
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[(set_attr "neon_type" "neon_vshl_ddd")]
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)
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;; ashrdi3_neon
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;; lshrdi3_neon
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(define_insn_and_split "<shift>di3_neon"
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[(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r,?w,?w")
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(rshifts:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r,0w, w")
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(match_operand:SI 2 "reg_or_int_operand" " r, i, r, i, r, i")))
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(clobber (match_scratch:SI 3 "=2r, X, &r, X,2r, X"))
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(clobber (match_scratch:SI 4 "= X, X, &r, X, X, X"))
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(clobber (match_scratch:DI 5 "=&w, X, X, X,&w, X"))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_NEON"
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"#"
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"TARGET_NEON && reload_completed"
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[(const_int 0)]
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"
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{
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if (IS_VFP_REGNUM (REGNO (operands[0])))
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{
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if (CONST_INT_P (operands[2]))
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{
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if (INTVAL (operands[2]) < 1)
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{
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emit_insn (gen_movdi (operands[0], operands[1]));
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DONE;
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}
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else if (INTVAL (operands[2]) > 64)
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operands[2] = gen_rtx_CONST_INT (VOIDmode, 64);
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/* Ditch the unnecessary clobbers. */
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emit_insn (gen_<shift>di3_neon_imm_noclobber (operands[0],
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operands[1],
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operands[2]));
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}
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else
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{
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/* We must use a negative left-shift. */
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emit_insn (gen_negsi2 (operands[3], operands[2]));
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emit_insn (gen_neon_load_count (operands[5], operands[3]));
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emit_insn (gen_<shifttype>_shift_di3_neon (operands[0], operands[1],
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operands[5]));
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}
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}
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else
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{
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if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
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/* This clobbers CC. */
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emit_insn (gen_arm_<shift>di3_1bit (operands[0], operands[1]));
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else
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/* This clobbers CC (ASHIFTRT by register only). */
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arm_emit_coreregs_64bit_shift (<CODE>, operands[0], operands[1],
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operands[2], operands[3], operands[4]);
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}
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DONE;
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}"
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[(set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")
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(set_attr "opt" "*,*,speed,speed,*,*")]
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)
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;; Widening operations
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(define_insn "widen_ssum<mode>3"
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