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combine cmps with shifts

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2009-08-24  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

       * gcc.target/arm/combine-cmp-shift.c: New test.

2009-08-24  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

       * config/arm/arm.c (arm_select_cc_mode): Handle subreg.

From-SVN: r151050
This commit is contained in:
Ramana Radhakrishnan 2009-08-24 09:03:35 +00:00 committed by Ramana Radhakrishnan
parent 54f52b8164
commit 3e2d9dcfa8
4 changed files with 27 additions and 2 deletions
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4
gcc/ChangeLog
View File

@ -1,3 +1,7 @@
2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm.c (arm_select_cc_mode): Handle subreg.
2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/vfp.md (*arm_movdi_vfp): Mark as predicable.

6
gcc/config/arm/arm.c
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@ -9504,7 +9504,8 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
/* A compare with a shifted operand. Because of canonicalization, the
comparison will have to be swapped when we emit the assembler. */
if (GET_MODE (y) == SImode && GET_CODE (y) == REG
if (GET_MODE (y) == SImode
&& (REG_P (y) || (GET_CODE (y) == SUBREG))
&& (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
|| GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
|| GET_CODE (x) == ROTATERT))
@ -9512,7 +9513,8 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
/* This operation is performed swapped, but since we only rely on the Z
flag we don't need an additional mode. */
if (GET_MODE (y) == SImode && REG_P (y)
if (GET_MODE (y) == SImode
&& (REG_P (y) || (GET_CODE (y) == SUBREG))
&& GET_CODE (x) == NEG
&& (op == EQ || op == NE))
return CC_Zmode;

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2009-08-11 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gcc.target/arm/combine-cmp-shift.c: New test.
2009-08-24 Kai Tietz <kai.tietz@onevision.com>
*gcc.dg/format/ms-format1.c: Add new cases for I32

15
gcc/testsuite/gcc.target/arm/combine-cmp-shift.c Normal file
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@ -0,0 +1,15 @@
/* { dg-options "-O2 -mcpu=cortex-a8" } */
/* { dg-final { scan-assembler "cmp\tr\[0-9\]*, r\[0-9\]*, asr #31" } } */
typedef int SItype __attribute__ ((mode (SI)));
typedef int DItype __attribute__ ((mode (DI)));
void abort (void);
SItype
__mulvsi3 (SItype a, SItype b)
{
const DItype w = (DItype) a * (DItype) b;
if ((SItype) (w >> (4 * 8)) != (SItype) w >> ((4 * 8) - 1))
abort ();
return w;
}