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altivec.md (altivec_vsr<VI_char>): Rename to ..

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* config/rs600/altivec.md (altivec_vsr<VI_char>): Rename to ..
         (lhsr<mode>3): ... new name.
         (altivec_vsra<VI_char>): Rename to ..
         (ashr<mode>3): ... new name.
         * config/rs6000/rs6000.c (builtin_description): Rename shift
         operations.

         testsuite:
         * lib/target-supports.exp (check_effective_target_vect_shif): New.
         * gcc.dg/vect/vect-shift-1.c: New test.

From-SVN: r97636
This commit is contained in:
Devang Patel 2005-04-05 09:33:29 -07:00 committed by Devang Patel
parent e72f3fa192
commit 3e0de9d188
6 changed files with 67 additions and 12 deletions
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9
gcc/ChangeLog
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@ -1,3 +1,12 @@
2004-04-05 Devang Patel <dpatel@apple.com>
* config/rs600/altivec.md (altivec_vsr<VI_char>): Rename to ..
(lhsr<mode>3): ... new name.
(altivec_vsra<VI_char>): Rename to ..
(ashr<mode>3): ... new name.
* config/rs6000/rs6000.c (builtin_description): Rename shift
operations.
2004-04-05 Paolo Bonzini <bonzini@gnu.org>
* combine.c (RTL_HOOKS_GEN_LOWPART_NO_EMIT): Use

12
gcc/config/rs6000/altivec.md
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@ -968,18 +968,18 @@
"vslo %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vsr<VI_char>"
(define_insn "lshr<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")] 112))]
(lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v") ))]
"TARGET_ALTIVEC"
"vsr<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vsra<VI_char>"
(define_insn "ashr<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")] 115))]
(ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v") ))]
"TARGET_ALTIVEC"
"vsra<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])

12
gcc/config/rs6000/rs6000.c
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@ -5590,12 +5590,12 @@ static struct builtin_description bdesc_2arg[] =
{ MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
{ MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
{ MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
{ MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
{ MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
{ MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
{ MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
{ MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2004-04-05 Devang Patel <dpatel@apple.com>
* lib/target-supports.exp (check_effective_target_vect_shif): New.
* gcc.dg/vect/vect-shift-1.c: New test.
2005-04-05 Francois-Xavier Coudert <coudert@clipper.ens.fr>
PR libfortran/20755

28
gcc/testsuite/gcc.dg/vect/vect-shift-1.c Normal file
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@ -0,0 +1,28 @@
/* { dg-require-effective-target vect_shift } */
#include <stdarg.h>
#include <signal.h>
#define N 16
#define MAX 42
extern void abort(void);
int main ()
{
unsigned int A[4] = {0x08000000,0x08000001,0xff0000ff,0xf0000001};
unsigned int Answer[4] = {0x01000000,0x01000000,0x01fe0001f,0x1e000000};
unsigned int B[4];
int i, j;
for (i=0; i<4; i++)
B[i] = A[i] >> 3;
for (i=0; i<4; i++)
if (B[i] != Answer[i])
abort ();
return 0;
}
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail i?86-*-* x86_64-*-* } } } */

13
gcc/testsuite/lib/target-supports.exp
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@ -640,6 +640,19 @@ proc check_effective_target_vect_int { } {
return $et_vect_int_saved
}
# Return 1 if the target supports hardware vector shift operation.
proc check_effective_target_vect_shift { } {
if { [istarget powerpc*-*-*] } {
set answer 1
} else {
set answer 0
}
verbose "check_effective_target_vect_shift: returning $answer" 2
return $answer
}
# Return 1 if the target supports hardware vectors of long, 0 otherwise.
#
# This can change for different subtargets so do not cache the result.