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aarch64-modes.def: Define ccmp CC mode.

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2014-11-17  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	* config/aarch64/aarch64-modes.def: Define ccmp CC mode.
	* config/aarch64/aarch64.c (aarch64_get_condition_code_1): New function
	extacted from aarch64_get_condition_code.
	(aarch64_get_condition_code): Call aarch64_get_condition_code_1.
	config/aarch64/predicates.md (ccmp_cc_register): New predicate.

From-SVN: r217643
This commit is contained in:
Zhenqiang Chen 2014-11-17 06:12:43 +00:00 committed by Zhenqiang Chen
parent b56d6aa18a
commit 3dfa7055cb
4 changed files with 102 additions and 0 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2014-11-17 Zhenqiang Chen <zhenqiang.chen@linaro.org>
* config/aarch64/aarch64-modes.def: Define ccmp CC mode.
* config/aarch64/aarch64.c (aarch64_get_condition_code_1): New function
extacted from aarch64_get_condition_code.
(aarch64_get_condition_code): Call aarch64_get_condition_code_1.
config/aarch64/predicates.md (ccmp_cc_register): New predicate.
014-11-17 Zhenqiang Chen <zhenqiang.chen@linaro.org>
* config/aarch64/constraints.md (Usn, aarch64_ccmp_immediate,

10
gcc/config/aarch64/aarch64-modes.def
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@ -25,6 +25,16 @@ CC_MODE (CC_ZESWP); /* zero-extend LHS (but swap to make it RHS). */
CC_MODE (CC_SESWP); /* sign-extend LHS (but swap to make it RHS). */
CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */
CC_MODE (CC_Z); /* Only Z bit of condition flags is valid. */
CC_MODE (CC_DNE);
CC_MODE (CC_DEQ);
CC_MODE (CC_DLE);
CC_MODE (CC_DLT);
CC_MODE (CC_DGE);
CC_MODE (CC_DGT);
CC_MODE (CC_DLEU);
CC_MODE (CC_DLTU);
CC_MODE (CC_DGEU);
CC_MODE (CC_DGTU);
/* Vector modes. */
VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI. */

67
gcc/config/aarch64/aarch64.c
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@ -3625,6 +3625,9 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
return CCmode;
}
static int
aarch64_get_condition_code_1 (enum machine_mode, enum rtx_code);
int
aarch64_get_condition_code (rtx x)
{
@ -3633,7 +3636,13 @@ aarch64_get_condition_code (rtx x)
if (GET_MODE_CLASS (mode) != MODE_CC)
mode = SELECT_CC_MODE (comp_code, XEXP (x, 0), XEXP (x, 1));
return aarch64_get_condition_code_1 (mode, comp_code);
}
static int
aarch64_get_condition_code_1 (enum machine_mode mode, enum rtx_code comp_code)
{
int ne = -1, eq = -1;
switch (mode)
{
case CCFPmode:
@ -3656,6 +3665,56 @@ aarch64_get_condition_code (rtx x)
}
break;
case CC_DNEmode:
ne = AARCH64_NE;
eq = AARCH64_EQ;
break;
case CC_DEQmode:
ne = AARCH64_EQ;
eq = AARCH64_NE;
break;
case CC_DGEmode:
ne = AARCH64_GE;
eq = AARCH64_LT;
break;
case CC_DLTmode:
ne = AARCH64_LT;
eq = AARCH64_GE;
break;
case CC_DGTmode:
ne = AARCH64_GT;
eq = AARCH64_LE;
break;
case CC_DLEmode:
ne = AARCH64_LE;
eq = AARCH64_GT;
break;
case CC_DGEUmode:
ne = AARCH64_CS;
eq = AARCH64_CC;
break;
case CC_DLTUmode:
ne = AARCH64_CC;
eq = AARCH64_CS;
break;
case CC_DGTUmode:
ne = AARCH64_HI;
eq = AARCH64_LS;
break;
case CC_DLEUmode:
ne = AARCH64_LS;
eq = AARCH64_HI;
break;
case CCmode:
switch (comp_code)
{
@ -3716,6 +3775,14 @@ aarch64_get_condition_code (rtx x)
return -1;
break;
}
if (comp_code == NE)
return ne;
if (comp_code == EQ)
return eq;
return -1;
}
bool

17
gcc/config/aarch64/predicates.md
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@ -38,6 +38,23 @@
(ior (match_operand 0 "register_operand")
(match_operand 0 "aarch64_ccmp_immediate")))
(define_special_predicate "ccmp_cc_register"
(and (match_code "reg")
(and (match_test "REGNO (op) == CC_REGNUM")
(ior (match_test "mode == GET_MODE (op)")
(match_test "mode == VOIDmode
&& (GET_MODE (op) == CC_DNEmode
|| GET_MODE (op) == CC_DEQmode
|| GET_MODE (op) == CC_DLEmode
|| GET_MODE (op) == CC_DLTmode
|| GET_MODE (op) == CC_DGEmode
|| GET_MODE (op) == CC_DGTmode
|| GET_MODE (op) == CC_DLEUmode
|| GET_MODE (op) == CC_DLTUmode
|| GET_MODE (op) == CC_DGEUmode
|| GET_MODE (op) == CC_DGTUmode)"))))
)
(define_predicate "aarch64_simd_register"
(and (match_code "reg")
(ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")