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Fix gcc.dg/vect/vect-shift-1.c failure.

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* config/ia64/vect.md (ashl<mode>3, ashr<mode>3, lshr<mode>3): Use
DImode not VECINT24 for operand 2.

From-SVN: r105113
This commit is contained in:
James E Wilson 2005-10-07 17:39:09 -07:00 committed by Jim Wilson
parent 4383bf26c3
commit 3dbb4dcecd
2 changed files with 6 additions and 3 deletions
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3
gcc/ChangeLog
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@ -1,5 +1,8 @@
2005-10-07 James E. Wilson <wilson@specifix.com>
* config/ia64/vect.md (ashl<mode>3, ashr<mode>3, lshr<mode>3): Use
DImode not VECINT24 for operand 2.
PR target/23644
* doc/invoke.texi (IA-64 Options, item -mtune): Renamed from
-mtune-arch.

6
gcc/config/ia64/vect.md
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@ -318,7 +318,7 @@
[(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
(ashift:VECINT24
(match_operand:VECINT24 1 "gr_register_operand" "r")
(match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
(match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
""
"pshl<vecsize> %0 = %1, %2"
[(set_attr "itanium_class" "mmshf")])
@ -327,7 +327,7 @@
[(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
(ashiftrt:VECINT24
(match_operand:VECINT24 1 "gr_register_operand" "r")
(match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
(match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
""
"pshr<vecsize> %0 = %1, %2"
[(set_attr "itanium_class" "mmshf")])
@ -336,7 +336,7 @@
[(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
(lshiftrt:VECINT24
(match_operand:VECINT24 1 "gr_register_operand" "r")
(match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
(match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
""
"pshr<vecsize>.u %0 = %1, %2"
[(set_attr "itanium_class" "mmshf")])